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Old 11-15-2006, 07:57 PM
Jhlw
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Default Getting Xilinx DMA SG working with peripheral

Hi All,

Does anyone have experience with getting Xilinx DMA SG working with a
peripheral?
When you create your user IP using Create/Import peripheral, you just
select DMA
and it adds it for you, but then what? I am using EDK 8.2.01i.

I have read ipif_dma_sg.pdf in C:\EDK\doc,
dma_sg.pdf in
C:\EDK\hw\XilinxProcessorIPLib\pcores\dma_sg_v2_01 _a\doc
and ipif_dma_sg.pdf in
C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_ipif_v1_ 23_e\doc\ipif_dma_sg
I have also looked for reference designs installed with EDK and on the
Xilinx website.

Does receive SG DMA not wait
for some kind of "receive data in buffer just arrived" bit before it
reads the
data to the FIFO from the address?? I have such a bit in my peripheral,
indicating data is ready to be read. If SG DMA does not work that way,
how would
it work? It does not seem reasonable that receive DMA would just
continue
reading from the address, because it might fill up memory with
duplicate receive
data! I could not find a description or an indication of the receive SG
DMA
philosophy or operation along these lines in the documentation or in
the
reference designs on the website. I could really use a good, detailed
writeup in
plain language!! Or even something that hints at everything so I can at
least
puzzle it out!! Did anybody locate a good writeup on the Xilinx website
about
this?
Also it would be really nice if the DMA SG read could be triggered only
by a
rising edge of such a "receive data ready in peripheral" bit!

Also it would be nice if transmit DMA SG could wait for such a bit (to
go low,
i.e., falling edge but I could add a rising edge signal for that)
before sending, as well.

Thanks in advance,
-James

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