I see all these references to my old article in XCell magazine, and I
enjoy the positive comments.
But: In almost all cases, there is no need for 50% duty cycle. The
natural 33/66% duty cycle of a simple divide-by-three circuit is
acceptable, especially at such low frequencies as 70 MHz.
Here is one of the simplest implementations:
Two flip-flops QA and QB, QA feeds the D-input of QB (shift register)
The NOR of QA and QB feeds the D input of QA.
This circuit also recovers from the illegal state of both QA and QB
being High.
Peter Alfke
On Jan 18, 9:26 am, "visiblepulse" <
[email protected]> wrote:
> module clock_div3
> (
> clock_in,
> clock_out
> );
>
> input clock_in;
> output clock_out;
>
> reg clock_out;
> reg [2:1] d_pos;
> reg [2:1] d_neg;
>
> always @ (posedge clock_in)
> case (d_pos)
> 2'b00: d_pos[2:1] <= 2'b01;
> 2'b01: d_pos[2:1] <= 2'b11;
> default: d_pos[2:1] <= 2'b00;
> endcase
>
> always @ (negedge clock_in)
> case (d_neg)
> 2'b00: if (d_pos[1]) d_neg[2:1] <= 2'b01;
> 2'b01: d_neg[2:1] <= 2'b10;
> default: d_neg[2:1] <= 2'b00;
> endcase
>
> always @ (posedge clock_in or posedge (d_neg[1] & !clock_in))
> if (d_neg[1] & !clock_in)
> clock_out <= 1'b0;
> else
> if (!d_pos[1]) clock_out <= 1'b1;
>
> endmodule