FPGA Central

Hi, I'm still working on creating a DDR interface for an OCM bus.

The problem I now face is the following: I need "shifted" clk signals.
I'm using a driver originally used for the PLB bus, which has those
shifted clks. Since I do not have enough knowledge or time to create
shifted clk's myself (The deadline is reaaaly close).
So I "borrowed" the clock signals from the PLB bus (Runs on the same
speed as the OCM bus, I thought I could give it a try .

But when I do this, the timing constrains aren't met. So I guess I need
to create my own shifted signals from the OCM clk (Which I'm not even
using right now)
Here is the timing constraint table:

----------------------------------------------------------------------
Constraint | Requested| Actual |LLvls
----------------------------------------------------------------------
NET "bufgp_10/IBUFG" PERIOD = 10 nS HI | N/A | N/A | N/A
GH 50.000000 % | | |
----------------------------------------------------------------------
PERIOD analysis for net "dcm_0/dcm_0/CLK0 | 10.000ns | 5.476ns| 17
_BUF" derived from NET "bufgp_10/IBUFG" | | |
PERIOD = 10 nS HIGH 50.000000 % | | |
----------------------------------------------------------------------
* TSCLK2CLK90_ocm_ddr_1 = MAXDELAY FROM TIM | 2.250ns | 3.931ns| 5
EGRP "PLB_Clk_ocm_ddr_1" TO TIMEGRP "Clk | | |
90_in_ocm_ddr_1" 2.250 nS | | |
----------------------------------------------------------------------
PATH "FROM CPUS THRU RST_GRP TO FFS" TIG | N/A | 1.810ns| 0
----------------------------------------------------------------------
PATH "FROM FFS THRU RST_GRP TO FFS" TIG | N/A | 1.445ns| 1
----------------------------------------------------------------------
PATH "FROM FFS THRU RST_GRP TO CPUS" TIG | N/A | 0.656ns| 0

The one with the * is the one giving the problem.

How can I easily make such a clock myself?
Btw, I'm using EDK 6.3 and working on the ML310 board. (Virtex 2pro)

Thanks in advance,

Jim Tuilman

[email protected] wrote:
> How can I easily make such a clock myself?
> Btw, I'm using EDK 6.3 and working on the ML310 board. (Virtex 2pro)
Use a DCM:

http://toolbox.xilinx.com/docsan/xil...html#wp1000992

cu,
Sean

Depending on the speed you need you can also slow down the clock by 4 and
run it through a 3 stage shift register, where each output stage will be
shifed by 90 degrees.

Clock = 0 degrees
stage 1 = 90 degrees
stage 2 = 180 degrees
stage 3 = 270 degrees

dbrown

<[email protected]> wrote in message
news:[email protected] oups.com...
> Hi, I'm still working on creating a DDR interface for an OCM bus.
>
> The problem I now face is the following: I need "shifted" clk signals.
> I'm using a driver originally used for the PLB bus, which has those
> shifted clks. Since I do not have enough knowledge or time to create
> shifted clk's myself (The deadline is reaaaly close).
> So I "borrowed" the clock signals from the PLB bus (Runs on the same
> speed as the OCM bus, I thought I could give it a try .
>
> But when I do this, the timing constrains aren't met. So I guess I need
> to create my own shifted signals from the OCM clk (Which I'm not even
> using right now)
> Here is the timing constraint table:
>
> ----------------------------------------------------------------------
> Constraint | Requested| Actual |LLvls
> ----------------------------------------------------------------------
> NET "bufgp_10/IBUFG" PERIOD = 10 nS HI | N/A | N/A | N/A
> GH 50.000000 % | | |
> ----------------------------------------------------------------------
> PERIOD analysis for net "dcm_0/dcm_0/CLK0 | 10.000ns | 5.476ns| 17
> _BUF" derived from NET "bufgp_10/IBUFG" | | |
> PERIOD = 10 nS HIGH 50.000000 % | | |
> ----------------------------------------------------------------------
> * TSCLK2CLK90_ocm_ddr_1 = MAXDELAY FROM TIM | 2.250ns | 3.931ns| 5
> EGRP "PLB_Clk_ocm_ddr_1" TO TIMEGRP "Clk | | |
> 90_in_ocm_ddr_1" 2.250 nS | | |
> ----------------------------------------------------------------------
> PATH "FROM CPUS THRU RST_GRP TO FFS" TIG | N/A | 1.810ns| 0
> ----------------------------------------------------------------------
> PATH "FROM FFS THRU RST_GRP TO FFS" TIG | N/A | 1.445ns| 1
> ----------------------------------------------------------------------
> PATH "FROM FFS THRU RST_GRP TO CPUS" TIG | N/A | 0.656ns| 0
>
> The one with the * is the one giving the problem.
>
> How can I easily make such a clock myself?
> Btw, I'm using EDK 6.3 and working on the ML310 board. (Virtex 2pro)
>
> Thanks in advance,
>
> Jim Tuilman
>