Howdy Simon,

I forgot to explain why I mentioned 99% slice usage... doing so

should help confirm your (correct) understanding of unrelated logic.

The tools actually output a message that explains unrelated logic:

NOTES:

Related logic is defined as being logic that shares connectivity -

e.g. two LUTs are "related" if they share common inputs.

When assembling slices, Map gives priority to combine logic that

is related. Doing so results in the best timing performance.

Unrelated logic shares no connectivity. Map will only begin

packing unrelated logic into a slice once 99% of the slices are

occupied through related logic packing.

Note that once logic distribution reaches the 99% level through

related logic packing, this does not mean the device is completely

utilized. Unrelated logic packing will then begin, continuing until

all usable LUTs and FFs are occupied. Depending on your timing

budget, increased levels of unrelated logic packing may adversely

affect the overall timing performance of your design.

(taken from

http://toolbox.xilinx.com/docsan/xil...sim0020_5.html)

So as you can see from the output message, until it reaches 99%, the

tools almost go out of their way to use up slices before starting to

work a bit harder and put things that don't share inputs together. If

your unrelated logic is 0%, there is still considerable headroom above

99%. It's only when unrelated logic packing auto-activates that you

need to be concerned about being over 99%, and even then, it varies

drasticly by design. Here is the output of one design I helped with a

few years ago in ISE 5.3.3i:

Logic Utilization:

Total Number Slice Registers: 10,129 out of 18,560 54%

Number of 4 input LUTs: 13,491 out of 18,560 72%

Logic Distribution:

Number of occupied Slices: 9,278 out of

9,280 99%

Number of Slices containing only related logic: 5,259 out of

9,278 56%

Number of Slices containing unrelated logic: 4,019 out of

9,278 43%

[note that it is ONLY saying that 43% of the used slices contain

unrelated logic... it isn't saying that utilization is 99% + 43%, or

anything like that]

BTW, this whole discussion about unrelated logic usage only applies if

you leave the -timing option for MAP turned off (at least in ISE 6.x or

7.x). If -timing is turned on, I believe that slice packing is done

differently such that you won't get an unrelated packing number... in

theend, with -timing you should get better results, but it keeps the

designer a little more in the dark about how full the design really is.

None of this changes the fact that since your total slice usage is less

than your target device, so it should fit with no problems.

Here is another explaination of unrelated logic:

http://www.xilinx.com/xlnx/xil_ans_d...PagePath=12191
Summary: in some instances, it can adversely affect routability or

routing delays. In short, it varies by design. :-)

Good luck,

Marc