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Old 12-17-2004, 07:43 PM
Brad Smallridge
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Default FIFO WREN RDEN and missing clock cycle

Hi folks,

I have run into this problem before, and I just can't put a handle on it. I
use the code before to generate read and write enable to store bit image
information into a fifo. The idea is that the read enable comes on one line
after the write enable no mater what line length is used. Works great
except, as far as I can tell, there is a skew in the image fifo. Seems on
the first line, the write enable comes on n cycles before the read enable,
as it should, but what is needed is the the read enable come on n-1 cycles
on only the first row, so that the fifo outputs the first bit of the first
row, at the same time the first bit of the second row is going into the
fifo.

This probably won't make any sense to anybody unless they have done image
processing. Does anyone have a clean explanation and solution?

Most of the meat is in the v2 process:

-- video signal synching
v1: process(clk,reset)
begin
if(reset='1') then
vline_1 <= '0';
vline_2 <= '0';
vframe_1 <= '0';
vframe_2 <= '0';
vin_1 <= (others=>'0');
elsif(clk'event and clk='1') then
vline_1 <= vline;
vline_2 <= vline_1;
vframe_1 <= vframe;
vframe_2 <= vframe_1;
vin_1 <= vin;
vin_2 <= vin_1;
vin_3 <= vin_2;
end if;
end process;

-- fifo read and write enable setup
v2: process(clk,reset)
begin
if(reset='1') then
fifowren <= '0';
fiforden <= '0';
elsif(clk'event and clk='1') then
if( vframe_2='0') then
fifowren <= '0';
fiforden <= '0';
elsif( vline_1='1' and vline_2='0') then
fifowren <='1';
if( fifowren='1') then
fiforden <= '1'; -- one line later
end if;
end if;
end if;
end process;

v3: process(clk,reset)
begin
if(reset='1') then
video_threshold <= '0';
elsif(clk'event and clk='1') then
if( vin_1 > 175 ) then
video_threshold <= '1';
else
video_threshold <= '0';
end if;
end if;
end process;

v4: process(clk,reset)
begin
if(reset='1') then
video_bits_1 <= (others=>'0');
video_bits_2 <= (others=>'0');
elsif(clk'event and clk='1') then
video_bits_1 <= fifodout;
video_bits_2 <= video_bits_1;
end if;
end process;

-- shift lines done here
fifodin(2 downto 1) <= fifodout(1 downto 0);
fifodin(0) <= video_threshold;

v5: process(clk,reset)
begin
if(reset='1') then
vout <= (others=>'0');
elsif(clk'event and clk='1') then
if( video_bits_2(1)='1' and video_bits_2(2)='1') then
vout <= "10101010";
else
vout <= vin_3;
end if;
end if;
end process;



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Old 12-20-2004, 09:26 PM
Brad Smallridge
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Posts: n/a
Default Re: FIFO WREN RDEN and missing clock cycle

Hi Brad,

This looks like fun. Could you answer the following questions:
1) what type of FIFO are you using, i.e. what is it's timing?

I'm running this presently on a Spartan 3 at 48Mhz. I also had
a similar problem with a Cypress design. I think the issue
is generic.

A Xilinx COREGEN based FIFO will store data when write enable is high and
the FIFO isn't full, it will put valid data only 1 clock cycle after
read_enable was asserted with the FIFO not empty.

2) will the line length be stable once you start running or can it vary from
line to line/frame to frame?

Yes, stable.

3) you do quite some registering of your signals, so let me double check:
you wan't the lines to align at the FIFO (or somewhere else) as long as the
first pixel of each line is properly aligned or do you have have other
latency/alignment requirements?

No other reqirements.

4) Flushing of the FIFO: does the FIFO has to flush itself or can I assume
continous operation (no care for the last line of data when you switch of
the source)?

Continuous.

5) Could you also give a bit more details on the relationships between the
input signals (same frequency, aligned, same line widths of each image)?

The vline comes on at the same time valid data is available at vin. This is
a pretty typical sensor or image format sinario.

I hope you don't mind me mailing you directly, but I have some bad
experiences with spam flooding my e-mail. You can reports without any
problem, just keep out anything that resembles my e-mail address. For
further conversation, I'd prefer to use my personal e-mail address (see
CC.

Kind regards,
Alvin.


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  #3 (permalink)  
Old 12-21-2004, 07:09 PM
Brad Smallridge
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Posts: n/a
Default Re: FIFO WREN RDEN and missing clock cycle

Hi Brad,

There is a FIFO overflow, I think. Let me explain wht I think I see:

When valid frame data is available (vframe_2 = '1'), you start saving data
on the rising edge of the line indicator (vline1 = '1' AND vline_2 = '0').
Once the second line starts, you start reading out the FIFO. If a frame has
H lines, you will have stored H lines, but only read out (H - 1)!

[ASCII graph, use fixed font]
______________________ ______________________
FRAME ___/ \___/ \___
__ __ __ __ __ __
LINE ______/ \___/ \___/ \_________/ \___/ \___/ \______
___________________ ___________________
WRITE ______/ \______/ \___
____________ ____________
READ _____________/ \_____________/ \___

The fix is to start reading out the FIFO at the same time as you start
writing it, except for the very first line that you store (because you have
to fill the FIFO with 1 line of data). You can use the same starting
condition, except that you have to check the FIFO for not being empty before
launching the reads. There are 2 possibilities to do this:
1) check the FIFO's empty flag
2) have a register that is reset along with the other registers and only set
by the write enable (less resources if the FIFO hasn't the empty flag by
default).

My next comment is on the robustness of your design: what happens when you
switch on the video source or when you reset your design while the source is
running? There is no reason you will start saving the data from the first
line in a frame: if you see the 3th line pulse in a frame first after reset,
the you will currently start storing there. The solution is to have an
additional enable register that is reset like the others and is set when
frame is low: as such, no line will be stored before you have seen frame
going low.

Combining my remarks should give you the following waves:

[ASCII graph, use fixed font]
___
RESET
\_________________________________________________ ____________________
_______________ ______________________ ______________________
FRAME \___/ \___/
\___
__ __ __ __ __ __ __ __
LINE __/ \___/ \_________/ \___/ \___/ \_________/ \___/ \___/
\______

__________________________________________________ ______
FRMen+ ________________/
___________________ ___________________
WRITE ______________________/ \______/
\___

_________________________________________________
nEMPT+ _______________________/
____________ ___________________
READ _____________________________/ \______/
\___

Summarised:
WRITE start at the first line of a frame
READ start at the first line of a frame that the FIFO is not empty

If you're still up to some comments: the delay of the signal driving the mux
of vin_3 and the "10101010" constant puzzles me: assuming 1 cycle delay
between fiforden and the data coming out of the FIFO, then vin_3 and
fifodout are nicely aligned. But you add 2 more delays in process v5 by
using video_bits_2. Is this what you need (you're shifting the decision 2
pixels)?
Likewise, when you're checking for the treshold of the lines (current - 2)
and (current - 3), did you consider the wrapping from the bottom line to top
line in the next frame?

Some very last suggestion: do you check the timing of your asynchronous
reset? Without a flipflop clocking this signal, you will have no control
over it and you risk all kind of trouble (meta-stability when violating
setup/recovery timing of the resetable flipflops, flipflops coming out of
reset in a different clock cycle). In an FPGA, it's safer to use a
synchronous reset and it won't cost you any more resources (see the FPGA
registers).

Kind regards,
Alvin.



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