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Readon 11-08-2007 02:15 PM

FIFO interface design
 
i want to read & write data to/from a fifo placed in fpga. MCU's
external bus is connected to the chip. I am using the sync-fifo ip of
Altera CycloneII. The data bus and control signal are connected to
fifo directly. it's unfortune that when i read once from bus, data
would be read twice from fifo because there are two clock rising edges
during read signal(low active) is resetted. I think it will read more
datas from fifo if the read signal is resetted long enough.
Is there any good design for fifo interface connecting on the
exteranl bus?


Dave Pollum 11-09-2007 01:07 AM

Re: FIFO interface design
 
On Nov 8, 8:15 am, Readon <[email protected]> wrote:
> i want to read & write data to/from a fifo placed in fpga. MCU's
> external bus is connected to the chip. I am using the sync-fifo ip of
> Altera CycloneII. The data bus and control signal are connected to
> fifo directly. it's unfortune that when i read once from bus, data
> would be read twice from fifo because there are two clock rising edges
> during read signal(low active) is resetted. I think it will read more
> datas from fifo if the read signal is resetted long enough.
> Is there any good design for fifo interface connecting on the
> exteranl bus?


Using a Synchronous FIFO implies that the read clock and the write
clock are in the same clock domain. Is your MCU supplying the FIFO's
clock or is the FPGA supplying the MCU's clock? If the clock sources
are different, then you either need an Asynchronous FIFO, or you need
to run the MCU and FPGA from the same clock.
HTH
-Dave Pollum


Readon 11-09-2007 02:25 AM

Re: FIFO interface design
 
On Nov 9, 8:07 am, Dave Pollum <[email protected]> wrote:
> On Nov 8, 8:15 am, Readon <[email protected]> wrote:
>
> > i want to read & write data to/from a fifo placed in fpga. MCU's
> > external bus is connected to the chip. I am using the sync-fifo ip of
> > Altera CycloneII. The data bus and control signal are connected to
> > fifo directly. it's unfortune that when i read once from bus, data
> > would be read twice from fifo because there are two clock rising edges
> > during read signal(low active) is resetted. I think it will read more
> > datas from fifo if the read signal is resetted long enough.
> > Is there any good design for fifo interface connecting on the
> > exteranl bus?

>
> Using a Synchronous FIFO implies that the read clock and the write
> clock are in the same clock domain. Is your MCU supplying the FIFO's
> clock or is the FPGA supplying the MCU's clock? If the clock sources
> are different, then you either need an Asynchronous FIFO, or you need
> to run the MCU and FPGA from the same clock.
> HTH
> -Dave Pollum


It is in different clock, i tried altera's asynchronous FIFO which
need two extra clock for reading.
is there any better solution?


Gabor 11-09-2007 03:54 AM

Re: FIFO interface design
 
On Nov 8, 8:25 pm, Readon <[email protected]> wrote:
> On Nov 9, 8:07 am, Dave Pollum <[email protected]> wrote:
>
>
>
> > On Nov 8, 8:15 am, Readon <[email protected]> wrote:

>
> > > i want to read & write data to/from a fifo placed in fpga. MCU's
> > > external bus is connected to the chip. I am using the sync-fifo ip of
> > > Altera CycloneII. The data bus and control signal are connected to
> > > fifo directly. it's unfortune that when i read once from bus, data
> > > would be read twice from fifo because there are two clock rising edges
> > > during read signal(low active) is resetted. I think it will read more
> > > datas from fifo if the read signal is resetted long enough.
> > > Is there any good design for fifo interface connecting on the
> > > exteranl bus?

>
> > Using a Synchronous FIFO implies that the read clock and the write
> > clock are in the same clock domain. Is your MCU supplying the FIFO's
> > clock or is the FPGA supplying the MCU's clock? If the clock sources
> > are different, then you either need an Asynchronous FIFO, or you need
> > to run the MCU and FPGA from the same clock.
> > HTH
> > -Dave Pollum

>
> It is in different clock, i tried altera's asynchronous FIFO which
> need two extra clock for reading.
> is there any better solution?



If your MCU is running much slower than the FPGA, you can use the
FPGA's internal clock to run the synchronous FIFO, and a little
state logic to generate the necessary (single cycle) pulses for
read and write from the MCU interface signals.


John Retta 11-09-2007 03:39 PM

Re: FIFO interface design
 

>
> If your MCU is running much slower than the FPGA, you can use the
> FPGA's internal clock to run the synchronous FIFO, and a little
> state logic to generate the necessary (single cycle) pulses for
> read and write from the MCU interface signals.


In this case, logic is simply an edge detect.

ie.

reg read_level_q;
wire fifo_read_trailing_edge_det = ~read_level & read_level_q;

always @ (posedge clk)
begin
read_level_q <= read_level;
end


--

Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

Colorado Based Xilinx Consultant

email : [email protected]
web : www.rtc-inc.com

Readon 11-10-2007 05:56 AM

Re: FIFO interface design
 
On Nov 9, 10:54 am, Gabor <[email protected]> wrote:
> On Nov 8, 8:25 pm, Readon <[email protected]> wrote:
>
>
>
> > On Nov 9, 8:07 am, Dave Pollum <[email protected]> wrote:

>
> > > On Nov 8, 8:15 am, Readon <[email protected]> wrote:

>
> > > > i want to read & write data to/from a fifo placed in fpga. MCU's
> > > > external bus is connected to the chip. I am using the sync-fifo ip of
> > > > Altera CycloneII. The data bus and control signal are connected to
> > > > fifo directly. it's unfortune that when i read once from bus, data
> > > > would be read twice from fifo because there are two clock rising edges
> > > > during read signal(low active) is resetted. I think it will read more
> > > > datas from fifo if the read signal is resetted long enough.
> > > > Is there any good design for fifo interface connecting on the
> > > > exteranl bus?

>
> > > Using a Synchronous FIFO implies that the read clock and the write
> > > clock are in the same clock domain. Is your MCU supplying the FIFO's
> > > clock or is the FPGA supplying the MCU's clock? If the clock sources
> > > are different, then you either need an Asynchronous FIFO, or you need
> > > to run the MCU and FPGA from the same clock.
> > > HTH
> > > -Dave Pollum

>
> > It is in different clock, i tried altera's asynchronous FIFO which
> > need two extra clock for reading.
> > is there any better solution?

>
> If your MCU is running much slower than the FPGA, you can use the
> FPGA's internal clock to run the synchronous FIFO, and a little
> state logic to generate the necessary (single cycle) pulses for
> read and write from the MCU interface signals.


unfortunately, the problem i met is on the contrary. MCU is much
faster then FPGA, about 4 times.


John Retta 11-10-2007 06:04 PM

Re: FIFO interface design
 
Readon wrote:
> On Nov 9, 10:54 am, Gabor <[email protected]> wrote:
>> On Nov 8, 8:25 pm, Readon <[email protected]> wrote:
>>
>>
>>
>>> On Nov 9, 8:07 am, Dave Pollum <[email protected]> wrote:
>>>> On Nov 8, 8:15 am, Readon <[email protected]> wrote:
>>>>> i want to read & write data to/from a fifo placed in fpga. MCU's
>>>>> external bus is connected to the chip. I am using the sync-fifo ip of
>>>>> Altera CycloneII. The data bus and control signal are connected to
>>>>> fifo directly. it's unfortune that when i read once from bus, data
>>>>> would be read twice from fifo because there are two clock rising edges
>>>>> during read signal(low active) is resetted. I think it will read more
>>>>> datas from fifo if the read signal is resetted long enough.
>>>>> Is there any good design for fifo interface connecting on the
>>>>> exteranl bus?
>>>> Using a Synchronous FIFO implies that the read clock and the write
>>>> clock are in the same clock domain. Is your MCU supplying the FIFO's
>>>> clock or is the FPGA supplying the MCU's clock? If the clock sources
>>>> are different, then you either need an Asynchronous FIFO, or you need
>>>> to run the MCU and FPGA from the same clock.
>>>> HTH
>>>> -Dave Pollum
>>> It is in different clock, i tried altera's asynchronous FIFO which
>>> need two extra clock for reading.
>>> is there any better solution?

>> If your MCU is running much slower than the FPGA, you can use the
>> FPGA's internal clock to run the synchronous FIFO, and a little
>> state logic to generate the necessary (single cycle) pulses for
>> read and write from the MCU interface signals.

>
> unfortunately, the problem i met is on the contrary. MCU is much
> faster then FPGA, about 4 times.
>


- Just for info purposes what is the fpga clk rate and MCU rate?
- What is the fastest clk available on pwb?
- Does the MCU provide a clk at all for this interface? ie synchronous
interface?

Personally, I like to have an FPGA clk that is faster than any of my
interfaces, or I use a clk from the fastest source on the pwb, and make
my logic synchronous to that source, or I hope that if I have a high
speed interface, there is an external clk that I can use, and limit the
use of this clk within the fpga to just that interface..

That being said you are where you are.

You might want to look at using the clk multiplier function in the
Cyclone. You will be able to generate a higher clk fpga rate than
you currently have, treat the read pulse asynchronously, and use the
trailing edge detect I previously described. Since it is now
asynchronous you will have to make the single FF, two FF and decode
your edge detect off of these signals.

--

Regards,
John Retta
Owner and Designer
Retta Technical Consulting Inc.

Colorado Based Xilinx Consultant

phone : 303.926.0068
email : [email protected]
web : www.rtc-inc.com

John_H 11-10-2007 06:53 PM

Re: FIFO interface design
 
Readon wrote:
> On Nov 9, 10:54 am, Gabor <[email protected]> wrote:
>> On Nov 8, 8:25 pm, Readon <[email protected]> wrote:
>>> On Nov 9, 8:07 am, Dave Pollum <[email protected]> wrote:
>>>> On Nov 8, 8:15 am, Readon <[email protected]> wrote:


>>>>> i want to read & write data to/from a fifo placed in fpga. MCU's
>>>>> external bus is connected to the chip. I am using the sync-fifo ip of
>>>>> Altera CycloneII. The data bus and control signal are connected to
>>>>> fifo directly. it's unfortune that when i read once from bus, data
>>>>> would be read twice from fifo because there are two clock rising edges
>>>>> during read signal(low active) is resetted. I think it will read more
>>>>> datas from fifo if the read signal is resetted long enough.
>>>>> Is there any good design for fifo interface connecting on the
>>>>> exteranl bus?


>>>> Using a Synchronous FIFO implies that the read clock and the write
>>>> clock are in the same clock domain. Is your MCU supplying the FIFO's
>>>> clock or is the FPGA supplying the MCU's clock? If the clock sources
>>>> are different, then you either need an Asynchronous FIFO, or you need
>>>> to run the MCU and FPGA from the same clock.
>>>> HTH
>>>> -Dave Pollum


>>> It is in different clock, i tried altera's asynchronous FIFO which
>>> need two extra clock for reading.
>>> is there any better solution?


>> If your MCU is running much slower than the FPGA, you can use the
>> FPGA's internal clock to run the synchronous FIFO, and a little
>> state logic to generate the necessary (single cycle) pulses for
>> read and write from the MCU interface signals.


> unfortunately, the problem i met is on the contrary. MCU is much
> faster then FPGA, about 4 times.


I can get 600 Mb/s connections on a $5 FPGA. I don't know any fast MCUs
though the front side bus on some embedded processors can get pretty fast.

It sounds like you have an extremely simple logic problem. The read
from the MCU is too wide compared to the sync FIFO's clock.

Change that! If you know that you'll only have one read during a read
signal from the MCU, use that information to only assert the read
control to the sync FIFO once. *Do not* connect the double-wide read
pulse directly to the MCU. This is very, very simple logic.

Marlboro 11-10-2007 08:00 PM

Re: FIFO interface design
 
On Nov 9, 10:56 pm, Readon <[email protected]> wrote:
> On Nov 9, 10:54 am, Gabor <[email protected]> wrote:
>
>
>
>
>
> > On Nov 8, 8:25 pm, Readon <[email protected]> wrote:

>
> > > On Nov 9, 8:07 am, Dave Pollum <[email protected]> wrote:

>
> > > > On Nov 8, 8:15 am, Readon <[email protected]> wrote:

>
> > > > > i want to read & write data to/from a fifo placed in fpga. MCU's
> > > > > external bus is connected to the chip. I am using the sync-fifo ip of
> > > > > Altera CycloneII. The data bus and control signal are connected to
> > > > > fifo directly. it's unfortune that when i read once from bus, data
> > > > > would be read twice from fifo because there are two clock rising edges
> > > > > during read signal(low active) is resetted. I think it will read more
> > > > > datas from fifo if the read signal is resetted long enough.
> > > > > Is there any good design for fifo interface connecting on the
> > > > > exteranl bus?

>
> > > > Using a Synchronous FIFO implies that the read clock and the write
> > > > clock are in the same clock domain. Is your MCU supplying the FIFO's
> > > > clock or is the FPGA supplying the MCU's clock? If the clock sources
> > > > are different, then you either need an Asynchronous FIFO, or you need
> > > > to run the MCU and FPGA from the same clock.
> > > > HTH
> > > > -Dave Pollum

>
> > > It is in different clock, i tried altera's asynchronous FIFO which
> > > need two extra clock for reading.
> > > is there any better solution?

>
> > If your MCU is running much slower than the FPGA, you can use the
> > FPGA's internal clock to run the synchronous FIFO, and a little
> > state logic to generate the necessary (single cycle) pulses for
> > read and write from the MCU interface signals.

>
> unfortunately, the problem i met is on the contrary. MCU is much
> faster then FPGA, about 4 times.- Hide quoted text -
>
> - Show quoted text -



Some how you need to synchronize your MCU read to the FIFO read clock
(edge detect as others said), then make sure the read connects to the
FIFO has 1 clock wide only

btw, building your own FIFO isn't difficult if the speed fairly "slow"







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