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Old 02-26-2006, 07:01 AM
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Default FIFO design

what is the difference in using DPRAM instead of RAM for asynchronous
FIFO design?

Is it necessary to use DPRAM for designing Asynchronous FIFO?

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Old 02-26-2006, 06:08 PM
Peter Alfke
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Default Re: FIFO design

A dual-port RAM is ideal, because you can dedicate one port to the
writing, and the other one to the reading, with no interaction between
them (until you go full or empty).Only the flag control is tricky.
With a single port RAM, you must arbitrate between the asynchronous
reading and writing, since the RAM can only perform one operation at a
A low-performance (<100 MHz) multi-Mega-bit FIFO might be best
implemented in a single-port dynamic RAM plus the external arbitration
logic. But in that DRAM you must then arbitrate between read, write,
and refresh. I would design this as a hierarchy of two small dual-port
RAM-based FIFOs at the write and read side, plus a large dynamic RAM
in the middle.
Peter Alfke, Xilinx

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