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Old 11-24-2007, 10:23 AM
zlotawy
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Default Fifo Block-RAM Xilinx ISE - port empty

Hello,
I have generated a block-ram based FIFO queue (2 independent clocks, 2
inputs, 1 output) with the use of Core Generator. In the creator I used
version without registered outputs (1 clock latency).


I tested it by this code:


process(P_I_CLK,P_I_RESET_N)
variable v_state : integer := 0;
variable licznikX : integer range 0 to 255 := 0;


begin
if P_I_RESET_N = '0' then
v_state :=0;

elsif P_I_CLK'event and P_I_CLK = '1' then
sig_set_counter<='0';
case v_state is

when 0 =>

sig_data_to_fifo <= sig_counter;
sig_set_counter<='1';
sig_push_fifo <= '1';
sig_pop_fifo <= '0';
v_state := 1 ;

when 1 =>
sig_data_to_fifo <= sig_counter;
sig_push_fifo <= '1';
sig_pop_fifo <= '0';
v_state := 2 ;

when 2 =>
sig_data_to_fifo <= sig_counter;

sig_push_fifo <= '0';
sig_pop_fifo <= '1';
v_state := 3 ;

when 3 =>
sig_data_to_fifo <= sig_counter;

sig_push_fifo <= '0';
sig_pop_fifo <= '1';
v_state := 4 ;


when 4 =>
sig_data_to_fifo <= sig_counter;
sig_push_fifo <= '0';
sig_pop_fifo <= '1';
v_state := 5 ;





when 5 =>
sig_data_to_fifo <= sig_counter;
sig_push_fifo <= '1';
sig_pop_fifo <= '1';
v_state := 6 ;





when 6 =>
sig_data_to_fifo <= sig_counter;
sig_push_fifo <= '1';
sig_pop_fifo <= '1';
v_state := 7 ;





when 7 =>
sig_data_to_fifo <= sig_counter;
sig_push_fifo <= '0';
sig_pop_fifo <= '1';
v_state := 8 ;



when 8 =>
sig_data_to_fifo <= sig_counter;
sig_push_fifo <= '0';
sig_pop_fifo <= '1';
v_state := 0 ;

when others =>
sig_data_to_fifo <= sig_counter;

sig_push_fifo <= '0';
sig_pop_fifo <= '0';
v_state := 0 ;

end case;
end if;
end process ;


Signal sig_counter is output of counter.

And I ran ChipScopePro. I shown this:
http://www.elektroda.pl/rtvforum/download.php?id=272487

On the picture signal sig_data_to_fifo equels sig_dane_do_fifo and signal
sig_data_from_fifo equels sig_dane_z_fifo.


Output of FIFO I think works well. But I do not understand how does fifo set
port EMPTY. Could anyone tell me that all is correctly?

Clock is 50MHz, device is virtex2pro.

Thanks,
zlotawy


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