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  #1 (permalink)  
Old 10-26-2007, 01:51 PM
fpgabuilder
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Default FPGA vs ASIC

When it comes to designing for fpgas or asics there are a lot of
guidelines/rules that need to be followed consistently between the
both. Yes! things dealing with verilog event queue, metastability and
asynchronous clock domains, etc. What I am wondering is what are the
key differences between the designs targeted toward one or the other.
Thought it may make an interesting discussion.

Some that come to mind are -

+ Number of logic levels between flops
+ Uniform delay through a lut vs different delays through nand gates.
Asic delays highly dependent on the synthesizer and coding style?
FPGAs more forgiving about how the combinatorial logic is coded?
+ Asynchronous resets in fpgas
+ Clock gating not as efficient in fpga therefore use flop enables.
Require changes to the coding style?
+ Others?

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  #2 (permalink)  
Old 10-26-2007, 03:31 PM
Jonathan Bromley
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Default Re: FPGA vs ASIC

On Fri, 26 Oct 2007 12:51:59 -0000, fpgabuilder
<[email protected]> wrote:

>When it comes to designing for fpgas or asics there are a lot of
>guidelines/rules that need to be followed consistently between the
>both. Yes! things dealing with verilog event queue, metastability and
>asynchronous clock domains, etc. What I am wondering is what are the
>key differences between the designs targeted toward one or the other.
>Thought it may make an interesting discussion.
>
>Some that come to mind are -
>
>+ Number of logic levels between flops
>+ Uniform delay through a lut vs different delays through nand gates.
>Asic delays highly dependent on the synthesizer and coding style?
>FPGAs more forgiving about how the combinatorial logic is coded?
>+ Asynchronous resets in fpgas
>+ Clock gating not as efficient in fpga therefore use flop enables.
>Require changes to the coding style?


All good questions, although some of your implied conclusions
are arguable at best.

>+ Others?


I'd suggest the following:
- cost per function (much higher in FPGA) vs.
NRE (much higher in ASIC)
- speed/density/power: cutting-edge ASIC will always win on
all three of these, but the configurability and low NRE of
FPGA may well win for many applications
- instant-on: most FPGAs need configuration on power-up, and
this can take some time; ASICs just need stable power rails
and a reset
- can't integrate custom analog functionality on an FPGA?

But you specifically talked about "designing for"; in that
case, I suspect your next big question should be about
large, fixed functions. If you want a multiplier, or a
memory, in an FPGA you need to use one of the available
preset configurations of a built-in hard macro. If you
don't have enough of those hard macros, tough luck.
By contrast, such functions in ASIC are usually provided
as parameterized library macros that can be built in any
reasonable size or shape, and in any number, up to the
device limits. And, of course, if you don't use some
hard-macro resource on an FPGA, it's just wasted.
The FPGA vendors work hard (and smart) to get the balance
about right for the majority of their customers, and to
keep the cost penalties reasonable for the others; but
the issue is definitely there.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #3 (permalink)  
Old 10-26-2007, 04:05 PM
Ray Andraka
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Default Re: FPGA vs ASIC

Jonathan Bromley wrote:

> - speed/density/power: cutting-edge ASIC will always win on
> all three of these, but the configurability and low NRE of
> FPGA may well win for many applications


This is only true when working in the same feature size. FPGAs tend to
be on the bleeding edge of process where ASIC starts usually lag behind
by at least one or two process generations. Generally speaking, a lag
of 2 generations puts a reasonably carefully executed FPGA design pretty
much on par with an ASIC design in terms of the speed/power/density.

Another factor to consider for FPGAs is that design errors do not
restart the design cycle clock the way an ASIC error can.
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  #4 (permalink)  
Old 10-26-2007, 04:10 PM
fpgabuilder
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Default Re: FPGA vs ASIC

On Oct 26, 7:31 am, Jonathan Bromley <[email protected]>
wrote:
> All good questions, although some of your implied conclusions
> are arguable at best.


such as?

>
> >+ Others?

>
> I'd suggest the following:
> - cost per function (much higher in FPGA) vs.
> NRE (much higher in ASIC)


In favor of fpga I would also put down less rigid market window/
size.

> - speed/density/power: cutting-edge ASIC will always win on
> all three of these, but the configurability and low NRE of
> FPGA may well win for many applications
> - instant-on: most FPGAs need configuration on power-up, and
> this can take some time; ASICs just need stable power rails
> and a reset
> - can't integrate custom analog functionality on an FPGA?
>
> But you specifically talked about "designing for"; in that
> case, I suspect your next big question should be about
> large, fixed functions. If you want a multiplier, or a
> memory, in an FPGA you need to use one of the available
> preset configurations of a built-in hard macro. If you
> don't have enough of those hard macros, tough luck.
> By contrast, such functions in ASIC are usually provided
> as parameterized library macros that can be built in any
> reasonable size or shape, and in any number, up to the
> device limits. And, of course, if you don't use some
> hard-macro resource on an FPGA, it's just wasted.
> The FPGA vendors work hard (and smart) to get the balance
> about right for the majority of their customers, and to
> keep the cost penalties reasonable for the others; but
> the issue is definitely there.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> [email protected]://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.


All good comments. But they are more related to the FPGA vs ASIC
trade studies... I am more interested in differences in design
practices...

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  #5 (permalink)  
Old 10-26-2007, 04:57 PM
Jonathan Bromley
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Default Re: FPGA vs ASIC

On Fri, 26 Oct 2007 15:10:25 -0000, fpgabuilder
<[email protected]> wrote:

>On Oct 26, 7:31 am, Jonathan Bromley wrote:
>> All good questions, although some of your implied conclusions
>> are arguable at best.

>
>such as?


"Uniform delay through a LUT" is some way off the truth
these days - fanout delay typically dominates over
LUT/gate internal delays, and in more recent processes
it's routing delay that matters even more; these issues
hit both ASIC and FPGA designers, albeit with many
differences of detail - as I'm sure you're aware.

"FPGAs more forgiving about how the combinatorial
logic is coded?" Not in my experience, for sure -
although of course almost all of that stuff is
the synthesis tool's problem, not the designer's.

But, to reiterate: interesting questions. All the
more interesting because the answers to them
continue to shift thanks to new FPGA, ASIC and
design tool technology.

> In favor of fpga I would also put down less
> rigid market window/size.


Indeed.

[...]
>All good comments. But they are more related to the FPGA vs ASIC
>trade studies... I am more interested in differences in design
>practices...


Well.... I think I know what you're getting at, but surely
awareness of market issues is a vital skill for designers,
and such issues have a huge influence on design practice?
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
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  #6 (permalink)  
Old 10-26-2007, 05:53 PM
John_H
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Default Re: FPGA vs ASIC

"Ray Andraka" <[email protected]> wrote in message
news:[email protected]
> Jonathan Bromley wrote:
>
>> - speed/density/power: cutting-edge ASIC will always win on
>> all three of these, but the configurability and low NRE of
>> FPGA may well win for many applications

>
> This is only true when working in the same feature size. FPGAs tend to be
> on the bleeding edge of process where ASIC starts usually lag behind by at
> least one or two process generations. Generally speaking, a lag of 2
> generations puts a reasonably carefully executed FPGA design pretty much
> on par with an ASIC design in terms of the speed/power/density.
>
> Another factor to consider for FPGAs is that design errors do not restart
> the design cycle clock the way an ASIC error can.


I'd add that IOs for new FPGAs easily outperform IOs for ASICs at a feature
size that allows a reasonable NRE. For the 0.18 and 0.15 micron ASICs, the
IOs just don't compete with FPGAs! With all the discussion on how ASICs can
perform better than FPGAs, I was lulled into a false sense of adequacy.
Compromising on I/O just sucks. Go Go FPGAs!


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  #7 (permalink)  
Old 10-26-2007, 11:51 PM
Jecel
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Default Re: FPGA vs ASIC

On Oct 26, 10:51 am, fpgabuilder wrote:
> + Others?


On an FPGA your logic will probably run half as fast as the block
memories while on an ASIC it is the other way around. This could lead
to different design styles.

-- Jecel

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  #8 (permalink)  
Old 10-27-2007, 08:39 AM
Thomas Stanka
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Default Re: FPGA vs ASIC

On 26 Okt., 14:51, fpgabuilder <[email protected]> wrote:
> When it comes to designing for fpgas or asics there are a lot of
> guidelines/rules that need to be followed consistently between the
> both.

[..]
> Some that come to mind are -
>
> + Number of logic levels between flops
> + Uniform delay through a lut vs different delays through nand gates.
> Asic delays highly dependent on the synthesizer and coding style?
> FPGAs more forgiving about how the combinatorial logic is coded?


I have a different experience. The points above are more a question of
how hard you squeece a technology than a question between ASIC and
FPGA. You can have relaxed designs in both where you don't have to
bother and you can have designs on the edge of the technology in
both. The only major difference for the points above I would agree is
when it comed to adders because nearly every actual fpga provides fast
carry logic which I haven't seen in ASIC so far. This means that in
ASIC you have a lot faster adders than ripple carry while in fpga you
will use the ripple carry in most cases.

> + Asynchronous resets in fpgas


????

> + Clock gating not as efficient in fpga therefore use flop

enables.

This is one of the most important changes. I have designs which are
implemented in asic and fpga and this is one of the most important
changes.

> + Others?


Whenever I have a relaxed design, I code in a way that fits for all.
If i need to squeeze the last out of the technology, my code depends
on the choosen tech-lib and wouldn't even be easy portable between
different technologies of the same vendor, so why bother between asic
and fpga?

bye Thomas

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  #9 (permalink)  
Old 10-27-2007, 05:08 PM
mk
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Default Re: FPGA vs ASIC

On Sat, 27 Oct 2007 00:39:05 -0700, Thomas Stanka
<[email protected]> wrote:

>when it comed to adders because nearly every actual fpga provides fast
>carry logic which I haven't seen in ASIC so far.


Almost all ASIC libraires I've used has a full adder in it which is
basically what a fast carry logic is in an FPGA where they have
hardwired full adders which don't need to be made from luts and don't
need the programmable interconnect. I'ts very easy to accomplish the
same in an ASIC.
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  #10 (permalink)  
Old 10-28-2007, 10:55 PM
Andrew FPGA
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Default Re: FPGA vs ASIC

Are Asics and FPGA's really that close?

The following paper by Kuon and Rose compares a 90nm standard cell
asic technology with a 90nm FPGA, and shows that the FPGA takes a 40x
density hit (only 20x if include FPGA hard macros), critical path
delay 3-4x slower, and dynamic power 12x more.

"Measuring the Gap between FPGAs and Asics", Kuon and Rose,
Proceedings of the 2006 ACM/SIGDA 14th international symposium on
Field programmable gate arrays. Abstract below.

They made the comparison by implementing the following design
elements.

Design, ALUTs, Total Memory, 9x9 Bits Multipliers
booth 68 0 0
rs encoder 703 0 0
cordic18 2 105 0 0
cordic8 455 0 0
des area 595 0 0
des perf 2 604 0 0
fir restruct 673 0 0
mac1 1 885 0 0
aes192 1 456 0 0
fir3 84 4 0
diffeq 192 24 0
diffeq2 288 24 0
molecular 8 965 128 0
rs decoder1 706 13 0
rs decoder2 946 9 0
atm 16 544 0 3 204
aes 809 0 32 768
aes inv 943 0 34 176
ethernet 2 122 0 9 216
serialproc 680 0 2 880
fir24 1 235 50 96
pipe5proc 837 8 2 304
raytracer 16 346 171 54 758


Abstract
This paper presents experimental measurements of the differences
between a 90nm CMOS FPGA and 90nm CMOS
Standard Cell ASICs in terms of logic density, circuit speed
and power consumption. We are motivated to make these
measurements to enable system designers to make better informed
choices between these two media and to give insight
to FPGA makers on the deficiencies to attack and thereby
improve FPGAs. In the paper, we describe the methodology
by which the measurements were obtained and we show that,
for circuits containing only combinational logic and flipflops,
the ratio of silicon area required to implement them in
FPGAs and ASICs is on average 40. Modern FPGAs also
contain "hard" blocks such as multiplier/accumulators and
block memories and we find that these blocks reduce this
average area gap significantly to as little as 21. The ratio
of critical path delay, from FPGA to ASIC, is roughly 3 to
4, with less influence from block memory and hard multipliers.
The dynamic power consumption ratio is approximately
12 times and, with hard blocks, this gap generally becomes
smaller.


> > This is only true when working in the same feature size. FPGAs tend to be
> > on the bleeding edge of process where ASIC starts usually lag behind by at
> > least one or two process generations. Generally speaking, a lag of 2
> > generations puts a reasonably carefully executed FPGA design pretty much
> > on par with an ASIC design in terms of the speed/power/density.

>
> > Another factor to consider for FPGAs is that design errors do not restart
> > the design cycle clock the way an ASIC error can.

>
> I'd add that IOs for new FPGAs easily outperform IOs for ASICs at a feature
> size that allows a reasonable NRE. For the 0.18 and 0.15 micron ASICs, the
> IOs just don't compete with FPGAs! With all the discussion on how ASICs can
> perform better than FPGAs, I was lulled into a false sense of adequacy.
> Compromising on I/O just sucks. Go Go FPGAs!



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  #11 (permalink)  
Old 10-29-2007, 06:09 PM
Philip Potter
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Default Re: FPGA vs ASIC

Andrew FPGA wrote:
> Are Asics and FPGA's really that close?
>
> The following paper by Kuon and Rose compares a 90nm standard cell
> asic technology with a 90nm FPGA, and shows that the FPGA takes a 40x
> density hit (only 20x if include FPGA hard macros), critical path
> delay 3-4x slower, and dynamic power 12x more.


The FPGAs and ASICs compared have the same feature size, in which case
it is to be expected that the ASICs will outperform. But the point being
made was the following:

>>> This is only true when working in the same feature size. FPGAs tend to be
>>> on the bleeding edge of process where ASIC starts usually lag behind by at
>>> least one or two process generations. Generally speaking, a lag of 2
>>> generations puts a reasonably carefully executed FPGA design pretty much
>>> on par with an ASIC design in terms of the speed/power/density.


IIRC Xilinx Virtex-5 is on a 45nm process. This allows for 4 times the
effective area that a 90nm process allows. It seems that if we scale the
results from the quoted paper, a 45nm FPGA will take only a 5x density
hit (allowing hard macros) compared to a 90nm ASIC. I don't know how
critical path delay or dynamic power scale with process size, but once
you get small enough static power becomes at least as important as
dynamic power due to leakage currents etc.

Phil
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  #12 (permalink)  
Old 10-29-2007, 06:15 PM
mk
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Default Re: FPGA vs ASIC

On Mon, 29 Oct 2007 17:09:15 +0000, Philip Potter
<[email protected]> wrote:

>IIRC Xilinx Virtex-5 is on a 45nm process.


No, Virtex-5 is 65nm. No foundry is selling 45nm production wafers
yet.
http://www.xilinx.com/products/silic...v4features.htm
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  #13 (permalink)  
Old 10-29-2007, 11:13 PM
Andrew FPGA
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Default Re: FPGA vs ASIC

>. It seems that if we scale the
> results from the quoted paper, a 45nm FPGA will take only a 5x density
> hit (allowing hard macros) compared to a 90nm ASIC.


I was not sure how gate size scales with silicon area used so I did
not do your calculation - but I certainly did not think 2 process
generations would give a 20x density improvement. Do you not think a
5x density difference is significant?

Also, they compared the FPGA to a standard cell asic. Presumably with
full custom the difference would be even greater. (and the NRE FPGA
advantage would be even greater too of course.)


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  #14 (permalink)  
Old 10-30-2007, 12:42 PM
Philip Potter
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Default Re: FPGA vs ASIC

Andrew FPGA wrote:
>> . It seems that if we scale the
>> results from the quoted paper, a 45nm FPGA will take only a 5x density
>> hit (allowing hard macros) compared to a 90nm ASIC.

>
> I was not sure how gate size scales with silicon area used so I did
> not do your calculation - but I certainly did not think 2 process
> generations would give a 20x density improvement. Do you not think a
> 5x density difference is significant?


A 5x density difference is significant but it is less significant than a
20x density difference. (As mk rightly points out, my 5x figure is based
on the faulty assumption that the FPGA is 45nm.) The point I was making
is that the paper you quoted compares FPGAs and ASICs on the same
process, which is often not the choice which a business will be given.

Gate density, dynamic power, and clock speed are only some of the
considerations a business will look at when choosing their
implementation technology. FPGAs have clear advantages over ASICs in
some areas, but as you have pointed out ASICs have advantages over FPGAs
in others.

> Also, they compared the FPGA to a standard cell asic. Presumably with
> full custom the difference would be even greater. (and the NRE FPGA
> advantage would be even greater too of course.)


Yes, you're probably correct here.
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  #15 (permalink)  
Old 10-30-2007, 03:10 PM
Andy
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Default Re: FPGA vs ASIC

On Oct 29, 12:15 pm, mk <kal*@dspia.*comdelete> wrote:
> On Mon, 29 Oct 2007 17:09:15 +0000, Philip Potter
>
> <[email protected]> wrote:
> >IIRC Xilinx Virtex-5 is on a 45nm process.

>
> No, Virtex-5 is 65nm. No foundry is selling 45nm production wafers
> yet.http://www.xilinx.com/products/silic...virtex/virtex5...


No FPGA foundry... Intel is selling 45nm quad core processors now.
Historically, processors and FPGAs are leading applications of the
latest, smallest geometry sizes (for general purpose logic, as opposed
to specific things like memory, etc.).

Andy

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  #16 (permalink)  
Old 10-30-2007, 04:42 PM
mk
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Default Re: FPGA vs ASIC

On Tue, 30 Oct 2007 07:10:49 -0700, Andy <[email protected]>
wrote:

>On Oct 29, 12:15 pm, mk <kal*@dspia.*comdelete> wrote:
>> On Mon, 29 Oct 2007 17:09:15 +0000, Philip Potter
>>
>> <[email protected]> wrote:
>> >IIRC Xilinx Virtex-5 is on a 45nm process.

>>
>> No, Virtex-5 is 65nm. No foundry is selling 45nm production wafers
>> yet.http://www.xilinx.com/products/silic...virtex/virtex5...

>
>No FPGA foundry... Intel is selling 45nm quad core processors now.


Intel is not a foundry ie it doesn't sell foundry services where
people can send them a design to be manufactured in their fabrication
facilities for a price. TSMC, UMC, Chartered and SMIC are examples of
foundries and none of them is selling production 45nm wafers at this
time.
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  #17 (permalink)  
Old 10-30-2007, 09:59 PM
glen herrmannsfeldt
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Default Re: FPGA vs ASIC

Andrew FPGA wrote:
(snip)

> Also, they compared the FPGA to a standard cell asic. Presumably with
> full custom the difference would be even greater. (and the NRE FPGA
> advantage would be even greater too of course.)


Is Sea-of-gates still available? I used to have the descriptions
of the libraries for them. For SOG, as I understand it, only one custom
mask is needed, over what it pretty much an array of transistors.
The timing isn't quite as good as standard cell, as the transistor
size can't be varied as much. It should be a lot cheaper, though.

-- glen

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  #18 (permalink)  
Old 10-30-2007, 10:46 PM
Thomas Stanka
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Default Re: FPGA vs ASIC

On 30 Okt., 16:42, mk <kal*@dspia.*comdelete> wrote:
> >No FPGA foundry... Intel is selling 45nm quad core processors now.

>
> Intel is not a foundry ie it doesn't sell foundry services where
> people can send them a design to be manufactured in their fabrication
> facilities for a price. TSMC, UMC, Chartered and SMIC are examples of
> foundries and none of them is selling production 45nm wafers at this
> time.



IBM claims to provide a 45 nm ASIC process(IBM Cu-45HP ASIC). I don't
know, if you could get a production start right now(if your device
would be ready for production), but it is offered to customers on
their homepage.

bye Thomas

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  #19 (permalink)  
Old 10-30-2007, 10:50 PM
Thomas Stanka
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Default Re: FPGA vs ASIC

On 27 Okt., 17:08, mk <kal*@dspia.*comdelete> wrote:
> On Sat, 27 Oct 2007 00:39:05 -0700, Thomas Stanka
>
> <[email protected]> wrote:
> >when it comed to adders because nearly every actual fpga provides fast
> >carry logic which I haven't seen in ASIC so far.

>
> Almost all ASIC libraires I've used has a full adder in it which is
> basically what a fast carry logic is in an FPGA where they have
> hardwired full adders which don't need to be made from luts and don't
> need the programmable interconnect. I'ts very easy to accomplish the
> same in an ASIC.


Is it only a fulladder gate, or a full adder (for given bitsize)?
The adders I've seen in ASIC libs provide no fast carry compared to
normal cell delay. But that has nothing to say, as I'm not that
experienced in comparing ASIC technologies.

bye Thomas

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  #20 (permalink)  
Old 10-31-2007, 05:04 AM
mk
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Default Re: FPGA vs ASIC

On Tue, 30 Oct 2007 14:46:40 -0700, Thomas Stanka
<[email protected]> wrote:

>On 30 Okt., 16:42, mk <kal*@dspia.*comdelete> wrote:
>> >No FPGA foundry... Intel is selling 45nm quad core processors now.

>>
>> Intel is not a foundry ie it doesn't sell foundry services where
>> people can send them a design to be manufactured in their fabrication
>> facilities for a price. TSMC, UMC, Chartered and SMIC are examples of
>> foundries and none of them is selling production 45nm wafers at this
>> time.

>
>
>IBM claims to provide a 45 nm ASIC process(IBM Cu-45HP ASIC). I don't
>know, if you could get a production start right now(if your device
>would be ready for production), but it is offered to customers on
>their homepage.


Here is a quote from their press release: "IBM SiGe BiCMOS 6WL design
kits are available now. IBM plans to have SiGe BiCMOS 5PAe design kits
available this summer and first design kits for CMOS 11LP Foundry
products later in 2007. The planned availability date for Cu-45HP ASIC
is in early 2008."

http://www-03.ibm.com/press/us/en/pr...ease/21648.wss
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  #21 (permalink)  
Old 10-31-2007, 05:15 AM
mk
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Default Re: FPGA vs ASIC

On Tue, 30 Oct 2007 14:50:44 -0700, Thomas Stanka
<[email protected]> wrote:

>On 27 Okt., 17:08, mk <kal*@dspia.*comdelete> wrote:
>> On Sat, 27 Oct 2007 00:39:05 -0700, Thomas Stanka
>>
>> <[email protected]> wrote:
>> >when it comed to adders because nearly every actual fpga provides fast
>> >carry logic which I haven't seen in ASIC so far.

>>
>> Almost all ASIC libraires I've used has a full adder in it which is
>> basically what a fast carry logic is in an FPGA where they have
>> hardwired full adders which don't need to be made from luts and don't
>> need the programmable interconnect. I'ts very easy to accomplish the
>> same in an ASIC.

>
>Is it only a fulladder gate, or a full adder (for given bitsize)?
>The adders I've seen in ASIC libs provide no fast carry compared to
>normal cell delay. But that has nothing to say, as I'm not that
>experienced in comparing ASIC technologies.


Xilinx fast carry logic path for v5 is described in this document
http://direct.xilinx.com/bvdocs/userguides/ug190.pdf page 193. As you
can see it is not a multi-bit carry lookahead or anything similarly
complicated. It's a hardwired implementation of a ripple carry logic
which can be duplicated using standard cell full adders relatively
easily.
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  #22 (permalink)  
Old 10-31-2007, 07:10 AM
Thomas Stanka
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Default Re: FPGA vs ASIC

On 31 Okt., 05:15, mk <kal*@dspia.*comdelete> wrote:
> On Tue, 30 Oct 2007 14:50:44 -0700, Thomas Stanka
>
>
>
> <[email protected]> wrote:
> >On 27 Okt., 17:08, mk <kal*@dspia.*comdelete> wrote:
> >> On Sat, 27 Oct 2007 00:39:05 -0700, Thomas Stanka

>
> >> <[email protected]> wrote:
> >> >when it comed to adders because nearly every actual fpga provides fast
> >> >carry logic which I haven't seen in ASIC so far.

>
> >> Almost all ASIC libraires I've used has a full adder in it which is
> >> basically what a fast carry logic is in an FPGA where they have
> >> hardwired full adders which don't need to be made from luts and don't
> >> need the programmable interconnect. I'ts very easy to accomplish the
> >> same in an ASIC.

>
> >Is it only a fulladder gate, or a full adder (for given bitsize)?
> >The adders I've seen in ASIC libs provide no fast carry compared to
> >normal cell delay. But that has nothing to say, as I'm not that
> >experienced in comparing ASIC technologies.

>
> Xilinx fast carry logic path for v5 is described in this documenthttp://direct.xilinx.com/bvdocs/userguides/ug190.pdfpage 193. As you
> can see it is not a multi-bit carry lookahead or anything similarly
> complicated. It's a hardwired implementation of a ripple carry logic
> which can be duplicated using standard cell full adders relatively
> easily.



Thankyou, I have no need to learn the details of the virtex5 carry
logic at the moment.
The point I'm on is that in the fpga technologies I know the carry
chain path has a much faster gate delay compared to the normal gate
delay.
This means you could do 8 to 16 bit adding in a pipeline running
nearly at max technology speed for FF-gate-FF, maybe you need more
time multiplexing the data before or after the adder stage than the
time you need for adding.
In ASIC I've only seen gates with the carry chain having a gate delay
compareable to a gate delay, this means, that a 16 bit ripple adder
won't be able to run anywhere near FF-gate-FF but needs something like
FF-17xgate-FF. In that case you will likely have the adder stage
dominating your pipeline frequency. You could only speed up a ripple
carry adder by placing it tight together, but this has to be done at
any timing critical path anyway.

bye Thomas

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  #23 (permalink)  
Old 10-31-2007, 07:49 AM
Kim Enkovaara
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Default Re: FPGA vs ASIC

Thomas Stanka wrote:

> Is it only a fulladder gate, or a full adder (for given bitsize)?
> The adders I've seen in ASIC libs provide no fast carry compared to
> normal cell delay. But that has nothing to say, as I'm not that
> experienced in comparing ASIC technologies.


There are also different adder implementations at the synthesis
tool level. For example Design compiler with proper libraries
supports following adders: ripple-carry, carry-look-ahead,
delay-optimized flexible parallel-prefix, brent-kung, conditional-sum
and ripple-carry-select.

--Kim
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  #24 (permalink)  
Old 10-31-2007, 03:44 PM
mk
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Posts: n/a
Default Re: FPGA vs ASIC

On Tue, 30 Oct 2007 23:10:39 -0700, Thomas Stanka
<[email protected]> wrote:

>On 31 Okt., 05:15, mk <kal*@dspia.*comdelete> wrote:
>> On Tue, 30 Oct 2007 14:50:44 -0700, Thomas Stanka
>>
>>
>>
>> <[email protected]> wrote:
>> >On 27 Okt., 17:08, mk <kal*@dspia.*comdelete> wrote:
>> >> On Sat, 27 Oct 2007 00:39:05 -0700, Thomas Stanka

>>
>> >> <[email protected]> wrote:
>> >> >when it comed to adders because nearly every actual fpga provides fast
>> >> >carry logic which I haven't seen in ASIC so far.

>>
>> >> Almost all ASIC libraires I've used has a full adder in it which is
>> >> basically what a fast carry logic is in an FPGA where they have
>> >> hardwired full adders which don't need to be made from luts and don't
>> >> need the programmable interconnect. I'ts very easy to accomplish the
>> >> same in an ASIC.

>>
>> >Is it only a fulladder gate, or a full adder (for given bitsize)?
>> >The adders I've seen in ASIC libs provide no fast carry compared to
>> >normal cell delay. But that has nothing to say, as I'm not that
>> >experienced in comparing ASIC technologies.

>>
>> Xilinx fast carry logic path for v5 is described in this documenthttp://direct.xilinx.com/bvdocs/userguides/ug190.pdfpage 193. As you
>> can see it is not a multi-bit carry lookahead or anything similarly
>> complicated. It's a hardwired implementation of a ripple carry logic
>> which can be duplicated using standard cell full adders relatively
>> easily.

>
>
>Thankyou, I have no need to learn the details of the virtex5 carry
>logic at the moment.

Then I'm not sure what we're discussing here but I'll try one more
time.

>The point I'm on is that in the fpga technologies I know the carry
>chain path has a much faster gate delay compared to the normal gate
>delay.


That's because "normal gate delay" is so slow because of the
programmable gates and routing.
Normally when one is designing custom adders, a carry ripple adder is
the slowest and smallest adder against which other more sophisticated
carry select, carry skip, carry lookahead etc. are judged. One can buy
more speed by paying with area and/or power by using one of these
architectures.
The fact that in an FPGA a dedicated carry ripple adder is the fastest
just shows the inefficiency of the fabric. But one gets
programmability with that inefficiency so the compromise usually works
out.
Actually what the FPGAs has should be named "dedicated/hard-wired
carry ripple logic & routing" as there is not much "fast" about it.
What would've been fast is if they added some carry look ahead logic.
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  #25 (permalink)  
Old 10-31-2007, 06:26 PM
Ray Andraka
Guest
 
Posts: n/a
Default Re: FPGA vs ASIC

mk wrote:

> Actually what the FPGAs has should be named "dedicated/hard-wired
> carry ripple logic & routing" as there is not much "fast" about it.
> What would've been fast is if they added some carry look ahead logic.


Within a CLB, there certainly is carry look-ahead. It is abstracted out
in the user's guides as an implementation detail that is not visible to
the user. Be assured however, that there is a carry look-ahead going on
in the physical hardware.
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