FPGA Central

i am quite a newbie in FPGA development.
my idea is build a SoC(System on Chip) which will be a Video/Audio
player based on FPGA(Xilinx Spartan 3E 1M gate count).
the video and audio decoders are Vorbis for audio and Theora for video
and will be almost hardware based as posible.
the desgin will have a Soft CPU for directing data from CF,reading the
fs and then output a bitstream to decoders.
the audio decoder will output all the data to a DAC(20bit or 24 bit for
better quality).
the video decoder will write to a RAM which will be the LCD
framebuffer.
the cpu also can write to the framebuffer but it will write over
decoder data so i will have some kind of osd when the decoder is
playing(like for remaining time,volume and other stuff).

from what i understand,doing a full ogg decoder on chip is madness so
what i have to do i build coproccessors that will do most of
clock-expensive and the software will use those coprocessors,right?

the storage will be a CF card which are damn cheap and can work as
IDEs.
the part i want to know if this is posible to be done in a FPGA.

i saw a guy that made a full Theora camera which use a encoder for
super-high resolutions(1024x768@30FPS-->1280x1024@15FPS) on a Spartan
2E which have a 300K gates.(that desgin is 96% of the FPGA,the article
is in linuxdevices)
so i guess a decoder that can decode 160x120-->640x480 @25FPS streams
will be alot smaller and could fit into a FPGA.

i could move all the ogg vorbis decoder to a ASIC vorbis decoder(they
exsist ) so saving the time about implenting the ogg vorbis format.

what you think,it is posible? which soft cpu(s) should i use,which
things the cpu need to preform real fast? is it posible on a
Spartan(development boards for spartan are damn cheap).
if it is important to someone the desgin(the final one) will be powered
with a LiPo battery

thx in advance

"urielka" <[email protected]> writes:
> i am quite a newbie in FPGA development.
> my idea is build a SoC(System on Chip) which will be a Video/Audio
> player based on FPGA(Xilinx Spartan 3E 1M gate count).

i am quite a newbie in structural engineering.
my idea is build a suspension bridge which will have ten lanes
of traffic over grand canyon.

> from what i understand,doing a full ogg decoder on chip is madness so
> what i have to do i build coproccessors that will do most of
> clock-expensive and the software will use those coprocessors,right?

You have to read the various Ogg specifications and figure out what
parts those are.

> the storage will be a CF card which are damn cheap and can work as
> IDEs.
> the part i want to know if this is posible to be done in a FPGA.

The CF interface is definitely possible in an FPGA. As for the rest,
probably yes, but it's not exactly the sort of project that is
recommended for a newbie.

> i could move all the ogg vorbis decoder to a ASIC vorbis decoder(they
> exsist ) so saving the time about implenting the ogg vorbis format.

Good idea.

> what you think,it is posible? which soft cpu(s) should i use,

Depends on what your performance and cost requirements are.

> which things the cpu need to preform real fast?

That's something you need to research.

> is it posible on a
> Spartan(development boards for spartan are damn cheap).

Spartan 3 or 3e should be good. A Virtex 4 offers a lot more
processing power, and the FPGA fabric is faster, but it costs a
lot more.

> if it is important to someone the desgin(the final one) will be powered
> with a LiPo battery

Not for very long.

I would think that for this application you'd be much better off using
an existing ARM SoC.

"urielka" <[email protected]> writes:
> from what i understand,doing a full ogg decoder on chip is madness so

Yep, and Andrey is definately a mad scientist:

http://www.linuxdevices.com/articles/AT3888835064.html

- a

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urielka wrote:
> my idea is build a SoC(System on Chip) which will be a Video/Audio
> player based on FPGA(Xilinx Spartan 3E 1M gate count).
> the video and audio decoders are Vorbis for audio and Theora for video
> and will be almost hardware based as posible.
....
> from what i understand,doing a full ogg decoder on chip is madness so
> what i have to do i build coproccessors that will do most of
> clock-expensive and the software will use those coprocessors,right?

I'd start here: http://oggonachip.sourceforge.net/

> what you think,it is posible? which soft cpu(s) should i use,which
> things the cpu need to preform real fast? is it posible on a

IIRC, the report from this project had some analysis on performance issues.
http://oggonachip.sourceforge.net/og...1.0/report.pdf

See also the short paper version:
http://raweb.informatik.uni-stuttgar...aper-iscas.pdf

I've just found this too, but have not read this one.
http://ietfec.oxfordjournals.org/cgi...8-A/8/2124.pdf

Martin