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  #1 (permalink)  
Old 11-28-2007, 02:56 PM
Mike
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Default FPGA not in boundary scan

Hi

I am using Impact and Xilinx Multilinx cable to communicate to my FPGA
board. I was able that the connection to the board is established, but
somehow I just see a CPLD instead of a Virtex II FPGA board. Anyone an
idea how to have access to the FPGA that is hosted on the board?

Cheers
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  #2 (permalink)  
Old 11-29-2007, 02:41 AM
John_H
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Default Re: FPGA not in boundary scan

Mike wrote:
> Hi
>
> I am using Impact and Xilinx Multilinx cable to communicate to my FPGA
> board. I was able that the connection to the board is established, but
> somehow I just see a CPLD instead of a Virtex II FPGA board. Anyone an
> idea how to have access to the FPGA that is hosted on the board?
>
> Cheers


Connect your cable to the JTAG chain that the FPGA is hooked up to.

You couldn't be much more vague. Whether it's a development board or
your own board, you should be able to find schematics. These schematics
may show the JTAG pins of the FPGA (TDI, TDO, TCLK, TRST or similar
names) either unconnected or connected to a specific JTAG connector or
JTAG chain. If you can identify which chain, you're on your way. If
you are connected to the correct chain and you don't see the device,
there's something wrong on the application side (not configuring things
properly?) rather than the hardware side.

- John_H
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  #3 (permalink)  
Old 11-29-2007, 09:57 AM
Mike
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Default Re: FPGA not in boundary scan

If
> you are connected to the correct chain and you don't see the device,
> there's something wrong on the application side (not configuring things
> properly?) rather than the hardware side.
>
> - John_H


Thanks John, yes the hardware side should be fine, I have correctly
connected all the pins and as I mentioned I can see one device but
the FPGA is missing. I am using ISE 7.1, probably there are issues with
using the Multilinx cable? Can anyone from the Xilinx guys give an
answer to that if the Multilinx cable works alright with the 7.1 version?
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  #4 (permalink)  
Old 11-29-2007, 02:23 PM
John_H
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Default Re: FPGA not in boundary scan

Mike wrote:
> If
>> you are connected to the correct chain and you don't see the device,
>> there's something wrong on the application side (not configuring
>> things properly?) rather than the hardware side.
>>
>> - John_H

>
> Thanks John, yes the hardware side should be fine, I have correctly
> connected all the pins and as I mentioned I can see one device but
> the FPGA is missing. I am using ISE 7.1, probably there are issues with
> using the Multilinx cable? Can anyone from the Xilinx guys give an
> answer to that if the Multilinx cable works alright with the 7.1 version?


To see only the CPLD, the FPGA must be IDENTIFIED and put into bypass.

The problem you've identified screams that something is very wrong, not
simply a matter of the cable.

Are you using Impact? Chipscope? Synplicity's Identify? If you have
anything else that does JTAG, get a second opinion.

Help us help you - please specify what board and what software.
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  #5 (permalink)  
Old 11-29-2007, 04:52 PM
Mike
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Default Re: FPGA not in boundary scan


> Are you using Impact? Chipscope? Synplicity's Identify? If you have
> anything else that does JTAG, get a second opinion.
>
> Help us help you - please specify what board and what software.


Oh I wish someone of you could help me a out a little bit . Anyway
I installed ISE 7.1 and the drivers for the ADM-XRC-II board on another
machine. I connected and installed the MultiLinx cable to the board and
used Impact to get the devices in the boundary scan. Again I can just
see the Xilinx xc9572xl CPLD in the boundary scan. According to section
6.3 of the ADM-XRC-II manual, the FPGA (VirtexII) and CPLD are on the
same JTAG chain, so both should be visible in the software:
http://www.alphadata.co.uk/pdf/ADM-X...r%20Manual.pdf

Any helpful comments are appreciated!
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  #6 (permalink)  
Old 11-29-2007, 04:55 PM
Mike
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Default Re: FPGA not in boundary scan

> Whether it's a development board or
> your own board, you should be able to find schematics. These schematics
> may show the JTAG pins of the FPGA (TDI, TDO, TCLK, TRST or similar
> names) either unconnected or connected to a specific JTAG connector or
> JTAG chain.


And yes, I have exactly set up this connections to the FPGA board which
should be fine but there is still just this one CPLD in my boundary scan!
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  #7 (permalink)  
Old 11-29-2007, 08:10 PM
Mike
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Default Re: FPGA not in boundary scan


> And yes, I have exactly set up this connections to the FPGA board which
> should be fine but there is still just this one CPLD in my boundary scan!


Alright, my mistake. Actually there is another JTAG interface hiden
between the two boards. With this one it should work.

Sorry for the confusion!
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  #8 (permalink)  
Old 11-29-2007, 09:34 PM
John_H
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Default Re: FPGA not in boundary scan

On Nov 29, 12:10 pm, Mike <[email protected]> wrote:
> > And yes, I have exactly set up this connections to the FPGA board which
> > should be fine but there is still just this one CPLD in my boundary scan!

>
> Alright, my mistake. Actually there is another JTAG interface hiden
> between the two boards. With this one it should work.
>
> Sorry for the confusion!


I'm glad you found the second JTAG chain. If you have any more
troubles, we should be able to help out better this next round. Happy
Hunting!
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