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  #1 (permalink)  
Old 11-14-2007, 02:46 PM
Herbert Kleebauer
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Default FPGA for hobby use

A few month ago I asked for a recommendation for FPGA (not a ready to use demo board)
which could be handled with simple home equipment. I got the link to:

http://www.enterpoint.co.uk/moelbryn/darnaw1.html

We ordered a few samples and did some experimenting. Here the documentation
for a simple 16 bit CPU implemented on the DARNAW1. It includes also a step by
step introduction which should allow anybody still unfamiliar with FPGA design
to implement the demo in less than a hour.

ftp://137.193.64.130/pub/mproz/mproz3_e.pdf (documentation)
ftp://137.193.64.130/pub/mproz/mproz3.zip (documentation + schematics)

Conclusion:
The board is great, not just an other demo board, but rather a package
converter from the FPG ball grid to a pin grid array with the necessary
voltage converters and program flash on board. Sadly the same can't be
said about the current Xilinx software (schematic editor + simulator),
so we will try to stay as long as possible with the X3000 chips and the
old Xilinx DOS software (with ViewLogic schematic entry + simulator).

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  #2 (permalink)  
Old 11-14-2007, 03:07 PM
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Default Re: FPGA for hobby use

On Nov 14, 9:46 am, Herbert Kleebauer <[email protected]> wrote:

> Sadly the same can't be
> said about the current Xilinx software (schematic editor + simulator),
> so we will try to stay as long as possible with the X3000 chips and the
> old Xilinx DOS software (with ViewLogic schematic entry + simulator).


The real problem is your insistence on using schematic entry for
things of moderate complexity.

Learn a hardware description language and your life will be much
easier.


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  #3 (permalink)  
Old 11-14-2007, 03:30 PM
Guenter Dannoritzer
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Default Re: FPGA for hobby use

[email protected] wrote:
> On Nov 14, 9:46 am, Herbert Kleebauer <[email protected]> wrote:
>
>> Sadly the same can't be
>> said about the current Xilinx software (schematic editor + simulator),
>> so we will try to stay as long as possible with the X3000 chips and the
>> old Xilinx DOS software (with ViewLogic schematic entry + simulator).

>
> The real problem is your insistence on using schematic entry for
> things of moderate complexity.
>
> Learn a hardware description language and your life will be much
> easier.


.... and after knowing your configuration, use a Makefile to run
implementation and say good bye to the gui.

http://www.dilloneng.com/documents/d...ds/gen_ise_sh/

Cheers,

Guenter
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  #4 (permalink)  
Old 11-14-2007, 03:31 PM
John Adair
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Default Re: FPGA for hobby use

I am pleased to have such a positive response to one of our products.

I am also pleased to say that as of this week Rev1.1 is shipping to
customers. The major change is the programing headers are changes to
2x7 2mm headers compatible with our own Prog2 cable and all of the
Xilinx cables with 2x7 ribbon cable. We also now have a limited stock
of Darnaw1 with XC3S1600E and XC3S1200 (I GRADE) fitted. They are not
on the shop website as yet but are available to anyone that needs the
different variants. Pricing etc are listed on our enginering web
pages.

I would also welcome any feedback on Darnaw1 from anyone that has seen
the product as we prepare to start the Darnaw2, and maybe even the
Darnaw3, designs. These wouldn't replace Darnaw1 but will cover
slightly different application areas albeit with the aim of a
compatible footprint within the product family.

John Adair
Enterpoint Ltd.

On 14 Nov, 14:46, Herbert Kleebauer <[email protected]> wrote:
> A few month ago I asked for a recommendation for FPGA (not a ready to use demo board)
> which could be handled with simple home equipment. I got the link to:
>
> http://www.enterpoint.co.uk/moelbryn/darnaw1.html
>
> We ordered a few samples and did some experimenting. Here the documentation
> for a simple 16 bit CPU implemented on the DARNAW1. It includes also a step by
> step introduction which should allow anybody still unfamiliar with FPGA design
> to implement the demo in less than a hour.
>
> ftp://137.193.64.130/pub/mproz/mproz3_e.pdf (documentation)ftp://137.193.64.130/pub/mproz/mproz3.zip (documentation + schematics)
>
> Conclusion:
> The board is great, not just an other demo board, but rather a package
> converter from the FPG ball grid to a pin grid array with the necessary
> voltage converters and program flash on board. Sadly the same can't be
> said about the current Xilinx software (schematic editor + simulator),
> so we will try to stay as long as possible with the X3000 chips and the
> old Xilinx DOS software (with ViewLogic schematic entry + simulator).



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  #5 (permalink)  
Old 11-14-2007, 03:50 PM
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Default Re: FPGA for hobby use

>The real problem is your insistence on using schematic entry for
>things of moderate complexity.
>
>Learn a hardware description language and your life will be much
>easier.


I'd agree with that, as practical advice.

Long-term, perhaps we'll expect better graphical tools. We have
text-based languages now partly because they are easier to define
accurately and because they exploit our familiarity with complex text
written in linear fashion (over several pages), so it's a practical
way to keep a complex design under control and to write it down.

We don't (yet) have comparable graphical tools, but perhaps that will
come. I'm not sure the Mona Lisa would be as good if Leonardo had
made it with a text-based graphics description language or that
Beethoven's Fifth Symphony has the same appeal when experienced as a
hex dump of the WAV file.
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  #6 (permalink)  
Old 11-14-2007, 06:04 PM
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Default Re: FPGA for hobby use

On Nov 14, 10:50 am, [email protected] wrote:

> Long-term, perhaps we'll expect better graphical tools. We have
> text-based languages now partly because they are easier to define
> accurately and because they exploit our familiarity with complex text
> written in linear fashion (over several pages), so it's a practical
> way to keep a complex design under control and to write it down.
>
> We don't (yet) have comparable graphical tools, but perhaps that will
> come. I'm not sure the Mona Lisa would be as good if Leonardo had
> made it with a text-based graphics description language


The problem is that you seem to want to use the graphical layout to
represent the wrong aspect of the design.

Schmetic level and HDL level entry both try to capture functionality,
but HDL level is far superior for managing the the kinds of complexity
involved in accomplishing real functionality.

If you want to do something graphical, do it at the system level. Use
something like Matlab & Simluink to describe what you want the FPGA to
do, and then use the HDL generation plugins. to make the FPGA actually
do it.

The possible case where FPGA-vendor-tool schematic entry might still
make sense is if you do all the actual implementation modules in HDL
code, but make your top level a system-block-diagram sort of
schematic.

Otherwise you're just trying to represent in messy pictures what is
much clearer in text.

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  #7 (permalink)  
Old 11-14-2007, 06:33 PM
Symon
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Default Re: FPGA for hobby use

<[email protected]> wrote in message
news:[email protected] ups.com...
>
> Otherwise you're just trying to represent in messy pictures what is
> much clearer in text.
>

Dear Whoeveryouare,
That statement may well be true in your case. However, I know of engineers
who say exactly the reverse!

Don't get me wrong, IMHO, large projects with experienced engineers are best
served by using a HDL. That said, there are circumstances where I believe
schematics have an advantage.

You already mentioned one of these cases, when you wrote about a block
diagram. Another case is when an engineer is first starting to use FPGAs.
This is the situation being discussed in this thread. The use of schematics
allows some rookie engineers to get a better grasp of how their circuits are
realised in the FPGA. The schematic can clearly show individual FFs and
gates. I'd suggest this is particularly true when engineeers are coming from
a software background. The schematic design flow is so different from
software development, it forces a different 'hardware' mindset. When these
same engineers 'progress' to RTL, the experience they've gained from the
circuit structures they've built with schematics is very useful.

YMMV.
Cheers, Syms.


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  #8 (permalink)  
Old 11-14-2007, 06:48 PM
Jim Granville
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Default Re: FPGA for hobby use

Herbert Kleebauer wrote:
> A few month ago I asked for a recommendation for FPGA (not a ready to use demo board)
> which could be handled with simple home equipment. I got the link to:
>
> http://www.enterpoint.co.uk/moelbryn/darnaw1.html
>
> We ordered a few samples and did some experimenting. Here the documentation
> for a simple 16 bit CPU implemented on the DARNAW1. It includes also a step by
> step introduction which should allow anybody still unfamiliar with FPGA design
> to implement the demo in less than a hour.
>
> ftp://137.193.64.130/pub/mproz/mproz3_e.pdf (documentation)
> ftp://137.193.64.130/pub/mproz/mproz3.zip (documentation + schematics)
>
> Conclusion:
> The board is great, not just an other demo board, but rather a package
> converter from the FPG ball grid to a pin grid array with the necessary
> voltage converters and program flash on board. Sadly the same can't be
> said about the current Xilinx software (schematic editor + simulator),
> so we will try to stay as long as possible with the X3000 chips and the
> old Xilinx DOS software (with ViewLogic schematic entry + simulator).


So, hundreds of man months of SW effort have seen a nett-step backwards ?
Can you elaborate on some of the drawbacks, and perhaps Xilinx can fix
them ?

-jg

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  #9 (permalink)  
Old 11-14-2007, 07:01 PM
Mike Treseler
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Default Re: FPGA for hobby use

Herbert Kleebauer wrote:

> The board is great, not just an other demo board, but rather a package
> converter from the FPG ball grid to a pin grid array with the necessary
> voltage converters and program flash on board. Sadly the same can't be
> said about the current Xilinx software (schematic editor + simulator),
> so we will try to stay as long as possible with the X3000 chips and the
> old Xilinx DOS software (with ViewLogic schematic entry + simulator).


Maybe John will do an altera board someday.
The quartus schematic capture is clean and solid.
The free simulator is also limited to waves,
but the licensed version has a very usable version of modelsim
and an rtl viewer that covers verilog and vhdl.

-- Mike Treseler
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  #10 (permalink)  
Old 11-14-2007, 07:41 PM
Ray Andraka
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Posts: n/a
Default Re: FPGA for hobby use

[email protected] wrote:

>
> Otherwise you're just trying to represent in messy pictures what is
> much clearer in text.
>


I don't entirely agree with you. Good use of hierarchy makes schematic
far clearer than text for many if not most circuits. It also
facilitates reuse, maintainability etc. The problem is most schematic
users don't make very good use of hierarchy at all, and the tools are of
little help there as well. Back when I used Viewlogic, I had
constructed a rather extensive library of 1 and 2 bit slices, of
components built up from those slices and of macro functions. I had
honed that system well enough so that the top level designs looked like
signal processing block diagrams, and as you worked down through the
hierarchy you got to progressively simpler elements. That methodology
also allowed me to put placement constraints in the design.

The real advantages to using an HDL are:
1) they are readable with just a text editor, and therefore can be
archived without also archiving the tool and the computer. This also
means version control is easier.

2) It is far easier to build parameterized objects with an HDL. This
provides a means for faster reuse. This is mainly a tools issue, since
nothing was really made to automate parameterized schematics.

3) Currently, the tools for HDL designs are far superior to the
schematic tools, mainly because that is where the effort has been
focused over the last decade.
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  #11 (permalink)  
Old 11-14-2007, 07:45 PM
John Adair
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Default Re: FPGA for hobby use

One of these days we might have an Altera based product. We have been
asked by various people to do one and my very able team could turn an
Altera product very quickly if we decided to do that. The current
record by the team for delivering a working main development board to
a customer is 18 days from start of development. Most of our
competitors couldn't probably get the spec written in that time. That
product is still in the range and shipping.

It's a kind of funny thing that over the years Enterpoint at various
points in time actually did more Altera based work that Xilinx. A long
time ago we considered joining Altera's ACAP but Xilinx's equivalent
at the time came up as a better deal at the same time and the rest is
history.

Back to the present and we have an exciting roll out of products
coming. We have just about caught up on things we have promised for a
while and December and January will start to see the release of things
we have not talked about yet in any detail. Some very different
concepts to appear as well as the nearly predictable. Our own PCIE
core is in beta and working well on our PCIE Broaddown4 and that will
drive PCIE based boards that are the predictable end of the set of
releases coming.

John Adair
Enterpoint Ltd.


On 14 Nov, 19:01, Mike Treseler <[email protected]> wrote:
> Herbert Kleebauer wrote:
> > The board is great, not just an other demo board, but rather a package
> > converter from the FPG ball grid to a pin grid array with the necessary
> > voltage converters and program flash on board. Sadly the same can't be
> > said about the current Xilinx software (schematic editor + simulator),
> > so we will try to stay as long as possible with the X3000 chips and the
> > old Xilinx DOS software (with ViewLogic schematic entry + simulator).

>
> Maybe John will do an altera board someday.
> The quartus schematic capture is clean and solid.
> The free simulator is also limited to waves,
> but the licensed version has a very usable version of modelsim
> and an rtl viewer that covers verilog and vhdl.
>
> -- Mike Treseler



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  #12 (permalink)  
Old 11-14-2007, 07:46 PM
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Default Re: FPGA for hobby use

On Nov 14, 1:33 pm, "Symon" <[email protected]> wrote:

> You already mentioned one of these cases, when you wrote about a block
> diagram. Another case is when an engineer is first starting to use FPGAs.
> This is the situation being discussed in this thread. The use of schematics
> allows some rookie engineers to get a better grasp of how their circuits are
> realised in the FPGA. The schematic can clearly show individual FFs and
> gates. I'd suggest this is particularly true when engineeers are coming from
> a software background. The schematic design flow is so different from
> software development, it forces a different 'hardware' mindset. When these
> same engineers 'progress' to RTL, the experience they've gained from the
> circuit structures they've built with schematics is very useful.


I still think this is a mistake on an order comparable to trying to
use LabView to wire up assembly language instructions into a useful
program.

There's a time and a place to learn about real circuit implementations
of simple computational structures and of state machines - made of
gates and flip flops, and of gates and flip flops made of
transistors. But that's not effectively how things work in an FPGA.
FPGAs run on logic equations, which are going to be re-interpreted
into the proprietary assortment of available doodads by the tools
anyway.

Nobody should be instantiating discrete gates in an FPGA (iobuffers
and other special ones exempted), instead they should be writing
equations - HDL code - that accomplish the intended function in a
concise and comprehensible way.

The problem with schematic entry is that it's instantation-centric.
If you are using your schematic at a block diagram level to wire up
big modules, that's good. But if you are using it at a detailed level
to instantiate gates in a real project (or even HDL to instantiate
them), that's just silly. You should be writing equations - but how
do you enter equations in a schematic?

This is probably one reason why state machine graphical entry exists -
it's still arguably a non-serious tool, but at least it's focused on
what the circuit is supposed to do, not the obscuring detail of how it
does it.


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  #13 (permalink)  
Old 11-14-2007, 07:52 PM
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Default Re: FPGA for hobby use

On Nov 14, 2:41 pm, Ray Andraka <[email protected]> wrote:
> [email protected] wrote:
>
> > Otherwise you're just trying to represent in messy pictures what is
> > much clearer in text.

>
> I don't entirely agree with you. Good use of hierarchy makes schematic
> far clearer than text for many if not most circuits.


Yes, good use. That's why I suggested a top-level block diagram
schematic made of HDL coded modules could be good. And yes, it's
extensible down the hierarchy to a degree. But sooner or later you
will get down to HDL modules, either your own or the vendor mega
function libraries.

> The problem is most schematic
> users don't make very good use of hierarchy at all


Exactly.

> The real advantages to using an HDL are:
> 1) they are readable with just a text editor, and therefore can be
> archived without also archiving the tool and the computer. This also
> means version control is easier.


That says to me that the graphical block diagrams should be complexity
constrained:

- they should be legible on a letter sized piece of paper (as well as
on your monitor without scrolling)

- they shouldn't take more than an hour to re-create from the paper,
either in a buggy new graphical tool or in a textual HDL

It's when people try to create complexity in the graphical
representations - by not using hierarchy - that their unsuitability
shows up.

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  #14 (permalink)  
Old 11-14-2007, 08:23 PM
Symon
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Posts: n/a
Default Re: FPGA for hobby use

Hi Chris,
I added some comments below.

<[email protected]> wrote in message
news:[email protected] ps.com...
> On Nov 14, 1:33 pm, "Symon" <[email protected]> wrote:
>
>> You already mentioned one of these cases, when you wrote about a block
>> diagram. Another case is when an engineer is first starting to use FPGAs.
>> This is the situation being discussed in this thread. The use of
>> schematics
>> allows some rookie engineers to get a better grasp of how their circuits
>> are
>> realised in the FPGA. The schematic can clearly show individual FFs and
>> gates. I'd suggest this is particularly true when engineeers are coming
>> from
>> a software background. The schematic design flow is so different from
>> software development, it forces a different 'hardware' mindset. When
>> these
>> same engineers 'progress' to RTL, the experience they've gained from the
>> circuit structures they've built with schematics is very useful.

>
> I still think this is a mistake on an order comparable to trying to
> use LabView to wire up assembly language instructions into a useful
> program.
>
> There's a time and a place to learn about real circuit implementations
> of simple computational structures and of state machines - made of
> gates and flip flops, and of gates and flip flops made of
> transistors. But that's not effectively how things work in an FPGA.
> FPGAs run on logic equations, which are going to be re-interpreted
> into the proprietary assortment of available doodads by the tools
> anyway.
>

OK, but the point I'm trying to make is that schematics can be a good tool
to learn how the circuit is implemented _in_an_FPGA_. The FPGA
implementation is different than, for example, a discrete logic
implementation or an ASIC implementation. When a designer knows how the
circuit will be implementated he can tailor his design to fit. The
correlation between what is drawn in the schematic and what ends up in the
FPGA's LUTs is closer than with an equivalent RTL design, helping the
beginner see which structures are good, and which are bad.
>
> Nobody should be instantiating discrete gates in an FPGA (iobuffers
> and other special ones exempted), instead they should be writing
> equations - HDL code - that accomplish the intended function in a
> concise and comprehensible way.
>

Usually this is true. However, some designs require extracting the fastest
possible timing from the FPGA, or the smallest resource usage. A designer
can code the design in RTL appropriately and hope the synthesis tool gets
the message or they can instantiate FPGA primitives in their RTL. It's my
contention that a designer who has a grounding of the underlying structure
of the FPGA will be at an advantage, and one way to get that knowledge is to
design as a beginner with schematics.
>
> The problem with schematic entry is that it's instantation-centric.
>

Which is my point. Sometimes instantiation is useful for the reasons I
outlined above.
>
> If you are using your schematic at a block diagram level to wire up
> big modules, that's good. But if you are using it at a detailed level
> to instantiate gates in a real project (or even HDL to instantiate
> them), that's just silly. You should be writing equations - but how
> do you enter equations in a schematic?
>

Again, a fair point. But the context of this thread is education, not 'real
projects', which, I think, changes what is 'good'.
>
> This is probably one reason why state machine graphical entry exists -
> it's still arguably a non-serious tool, but at least it's focused on
> what the circuit is supposed to do, not the obscuring detail of how it
> does it.
>
>

I've never used state machine graphical entry, I can't comment.

Regards, Syms.



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  #15 (permalink)  
Old 11-14-2007, 08:50 PM
Guest
 
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Default Re: FPGA for hobby use

On Nov 14, 3:23 pm, "Symon" <[email protected]> wrote:
> OK, but the point I'm trying to make is that schematics can be a good tool
> to learn how the circuit is implemented _in_an_FPGA_.


No they can't. Unless you are dealing strictly in terms of vendor
megafunctions (and often even then), what you see or enter gets
completely refactored by the tools when they go to implement what
you've asked for.

In contrast, something like a minimum sum of products expression,
which students should learn to write by hand, is actually quite close
to what really happens in a primitive PAL type architecture.

Not that I'm arguing for HDL coding in MSP either - put in the
unsimplified expressions that describe what you want; the tools are
better at simplifying them (hand in hand with duplicating and
expanding for fanout and speed) than you are.

> The
> correlation between what is drawn in the schematic and what ends up in the
> FPGA's LUTs is closer than with an equivalent RTL design, helping the
> beginner see which structures are good, and which are bad.


Define "bad".

Some things that are simple to enter will get expanded, but sometimes
the expansion is an intentional optimization to compensate for fanout
or propogation delay. You shouldn't design for that. Design simple
expressions, which are what the tools are tested to compile.

> > Nobody should be instantiating discrete gates in an FPGA (iobuffers
> > and other special ones exempted), instead they should be writing
> > equations - HDL code - that accomplish the intended function in a
> > concise and comprehensible way.

>
> Usually this is true. However, some designs require extracting the fastest
> possible timing from the FPGA, or the smallest resource usage. A designer
> can code the design in RTL appropriately and hope the synthesis tool gets
> the message or they can instantiate FPGA primitives in their RTL.


You can't outsmart the tools by hand coding the general logic of your
design entry like that, as they will refactor what you've done
anyway. If you want something, you get it by using the constraints
interface to the tools to specify what you need.

> It's my
> contention that a designer who has a grounding of the underlying structure
> of the FPGA will be at an advantage, and one way to get that knowledge is to
> design as a beginner with schematics.


For architectures of the past, yes. For todays' architectures, the
only designers who understand the underlying structure in the
necessary details are those privy to the silicon vendor's trade
secrets. Everybody else gets to work with the interface they provide
- and most of their effort goes into the HDL interface and constraints
mechanism, not the schematic entry.

> Which is my point. Sometimes instantiation is useful for the reasons I
> outlined above.


Except that when you are coding the ficticious architecture offered,
mostly you are fooling yourself.


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  #16 (permalink)  
Old 11-14-2007, 09:37 PM
Mike Treseler
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Posts: n/a
Default Re: FPGA for hobby use

[email protected] wrote:
> On Nov 14, 3:23 pm, "Symon" <[email protected]> wrote:
>> OK, but the point I'm trying to make is that schematics can be a good tool
>> to learn how the circuit is implemented _in_an_FPGA_.

>
> No they can't. Unless you are dealing strictly in terms of vendor
> megafunctions (and often even then), what you see or enter gets
> completely refactored by the tools when they go to implement what
> you've asked for.


Any FPGA design source other than
a pure technology netlist is
completely refactored by the tools.
It's all abstraction.

The subject says "FPGA for hobby use".

If I fixed up cars for fun, I might
not want to also own a machine shop.

If I wanted to invest a few hours
wiring up some pseudo-TTL blocks
on a schematic just to make an LED flash,
I might just do it.
No worse than crossword puzzles or
posting on usenet

-- Mike Treseler
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  #17 (permalink)  
Old 11-14-2007, 09:38 PM
Symon
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Posts: n/a
Default Re: FPGA for hobby use

<[email protected]> wrote in message
news:[email protected] ups.com...
> On Nov 14, 3:23 pm, "Symon" <[email protected]> wrote:
>> OK, but the point I'm trying to make is that schematics can be a good
>> tool
>> to learn how the circuit is implemented _in_an_FPGA_.

>
> No they can't. Unless you are dealing strictly in terms of vendor
> megafunctions (and often even then), what you see or enter gets
> completely refactored by the tools when they go to implement what
> you've asked for.
>

I disagree! Because I know that FPGAs consist of 4 input LUTs that feed FFs,
I can design pipelined structures that are faster and smaller than if I had
no clue as to how the logic is implemented in an FPGA.
>
> Not that I'm arguing for HDL coding in MSP either - put in the
> unsimplified expressions that describe what you want; the tools are
> better at simplifying them (hand in hand with duplicating and
> expanding for fanout and speed) than you are.
>

Speak for yourself! ;-)
>
>> The
>> correlation between what is drawn in the schematic and what ends up in
>> the
>> FPGA's LUTs is closer than with an equivalent RTL design, helping the
>> beginner see which structures are good, and which are bad.

>
> Define "bad".
>

Slower, bigger, longer P&R, ...
>
> Some things that are simple to enter will get expanded, but sometimes
> the expansion is an intentional optimization to compensate for fanout
> or propogation delay. You shouldn't design for that. Design simple
> expressions, which are what the tools are tested to compile.
>
>
> You can't outsmart the tools by hand coding the general logic of your
> design entry like that, as they will refactor what you've done
> anyway. If you want something, you get it by using the constraints
> interface to the tools to specify what you need.
>

Again, please speak for yourself. I can and do 'outsmart' the tools,
particularly in pipelined designs. If I structure my VHDL so it can pipeline
logic that neatly fits the 4 LUT followed by a FF, my design has fewer space
and timing problems, and P&R runs faster. Or, if I code my design so that a
clock enable signal gets routed directly to the FFs CE pin, I can take
advantage of multi-cycle paths much more easily.
>
>
> For architectures of the past, yes. For todays' architectures, the
> only designers who understand the underlying structure in the
> necessary details are those privy to the silicon vendor's trade
> secrets. Everybody else gets to work with the interface they provide
> - and most of their effort goes into the HDL interface and constraints
> mechanism, not the schematic entry.
>
>> Which is my point. Sometimes instantiation is useful for the reasons I
>> outlined above.

>
> Except that when you are coding the ficticious architecture offered,
> mostly you are fooling yourself.
>
>

I think that's nonsense. The basic structure of a V4 FPGA is still a 4-LUT
followed by a FF the same as it was in an XC3000 20 years ago.
To illustrate, here's a problem where you can search C.A.F. for examples.
Population count. A circuit to count the number of '1's in a vector. If you
know the FPGA is made of 4-LUTs you can do a much better job of coding it
than if you don't.

Anyway, I see from Google you had a brief exchange on a similar subject on
comp.arch.embedded Oct.3rd with Ray Andraka. If he didn't change your mind,
I'm sure I'm wasting my time also. :-(
This thread is getting way off topic, and I think I've outlined my position
fairly clearly.

Good luck, Syms.


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  #18 (permalink)  
Old 11-14-2007, 11:30 PM
Guest
 
Posts: n/a
Default Re: FPGA for hobby use

>The problem is that you seem to want to use the graphical layout to
>represent the wrong aspect of the design.


>...HDL level is far superior for managing the the kinds of complexity
>involved in accomplishing real functionality


I don't want to use graphical layout at all. As I suggested, the
tools aren't yet good enough, so I feel much more comfortable with
text.

But we would be wrong to suggest that text communication is "far
superior" a priori. That makes as much sense as saying that GOTO is
bad "a priori". In both cases, it's just good practical advice in
certain circumstances. Some engineers (perhaps including the original
poster) will always feel more comfortable with a graphical
representation. It makes it possible, after all, to take in at a
glance a great deal more of the "complexity" which you mention. I
don't see that text (as we know it) will ever achieve that. Apart
from syntax colouring and screens bigger than 80x25, we're just where
we were 30 years ago.

If you listen to Swahili for a week, you might conclude that it's not
a practical means of communication. That doesn't mean that others
won't find it perfectly usable (and preferable to your method, which
they might find intolerably complex). This isn't because either side
is right. It's because it's impossible properly to evaluate
alternative systems until you've used both a great deal and, even
then, your preference depends on you. The comfort you feel with
what's familiar and the discomfort with what isn't are not a good
basis for comparison.
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  #19 (permalink)  
Old 11-15-2007, 03:36 AM
Alex Colvin
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Default Re: FPGA for hobby use

>Long-term, perhaps we'll expect better graphical tools. We have
>text-based languages now partly because they are easier to define
>accurately and because they exploit our familiarity with complex text


Experience from software systems is that graphical tools don't scale to
large systems. The trick is to reduce a complex system to a few components
that can be glued together with graphical tools.

--
mac the naf
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  #20 (permalink)  
Old 11-15-2007, 04:15 AM
Joseph H Allen
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Posts: n/a
Default Re: FPGA for hobby use

I just want to say that old DOS OrCAD plus old Xilinx "Xblox" ended up being
very quick and very abstract, even if you are instaniating things instead of
synthesizing them. First, DOS OrCAD is *still* the best schematic editor
(which is just pathetic but true- compare it with Cadance Concept). Second,
Xblox adds the abstraction. It worked like this- there is for example and
adder component. A parameter on the adder sets its width. Wires are used
for busses instead of OrCAD busses, which means to change the width you only
have to mess with the parameters and not a bunch of bus labels.

Also I will point out that ASICs generally use synthesis but high end CPUs
tend to use all hand instantiation (no Verilog case statements allowed).
This makes hand layout and especially gate-level patches easier.
--
/* [email protected] AB1GO */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0%79-77?1:0<1659?79:0>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
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  #21 (permalink)  
Old 11-15-2007, 08:40 AM
Herbert Kleebauer
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Default Re: FPGA for hobby use

[email protected] wrote:
> On Nov 14, 9:46 am, Herbert Kleebauer <[email protected]> wrote:
>
> > Sadly the same can't be
> > said about the current Xilinx software (schematic editor + simulator),
> > so we will try to stay as long as possible with the X3000 chips and the
> > old Xilinx DOS software (with ViewLogic schematic entry + simulator).

>
> The real problem is your insistence on using schematic entry for
> things of moderate complexity.
>
> Learn a hardware description language and your life will be much
> easier.


That's no alternative. At the time of the course, the students know
about logic gates, flip-flops, how to minimize a logic equation and
how to design a simple state machine. And then there are exactly 10 hours
form reading the processor specification till the download of the
bit stream into the FPGA. This includes the time to get used to the
development software. And most of them will never do any hardware
design later anymore. But this year we will let one group use the new
Xilinx software, so we will see what's happen.
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  #22 (permalink)  
Old 11-15-2007, 08:41 AM
Herbert Kleebauer
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Default Re: FPGA for hobby use

Jim Granville wrote:
> Herbert Kleebauer wrote:


> > voltage converters and program flash on board. Sadly the same can't be
> > said about the current Xilinx software (schematic editor + simulator),
> > so we will try to stay as long as possible with the X3000 chips and the
> > old Xilinx DOS software (with ViewLogic schematic entry + simulator).

>
> So, hundreds of man months of SW effort have seen a nett-step backwards ?
> Can you elaborate on some of the drawbacks, and perhaps Xilinx can fix
> them ?


- I had more crashes with ISI 9.2 in the last few weeks than I have seen
in 10 years laboratory course with the old XILINX DOS software

- The essential drawback is the missing back annotation of the simulation
results into the schematic. This is like debugging software with print
statements instead of a source code debugger. A few years ago I tested
an older version (I think it was ISI 2.1) and there at least you could
attach probes in the schematic to display the states of signals.
This also was only a makeshift, but better than nothing.

- To much of the screen is wasted with the different windows. There should
be a full screen mode for the editor with keyboard commands and no menus
at all (only hidden pull down menus).

- I think the documentation has to be improved. If you have to use Google
to find some information, then something is wrong with the documentation.
Had real problems to find out how to update the bit stream with a new memory
content using data2mem.exe. This was also because of some very poor error
messages generated by the software.

- There also could be some improvement in the user interface, but this
always depends on user preferences. Does Xilinx have a quality feed
back program where customers are asked for suggestion for improvements?
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  #23 (permalink)  
Old 11-15-2007, 02:27 PM
Brian Drummond
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Posts: n/a
Default Re: FPGA for hobby use

On Wed, 14 Nov 2007 15:46:03 +0100, Herbert Kleebauer <[email protected]>
wrote:

>A few month ago I asked for a recommendation for FPGA (not a ready to use demo board)
>which could be handled with simple home equipment. I got the link to:
>
>http://www.enterpoint.co.uk/moelbryn/darnaw1.html


>Conclusion:
>The board is great, [...] Sadly the same can't be
>said about the current Xilinx software (schematic editor + simulator),
>so we will try to stay as long as possible with the X3000 chips and the
>old Xilinx DOS software (with ViewLogic schematic entry + simulator).


Is there any technology-independent way out of the Viewlogic/Dos
software? Such as a fairly generic EDIF netlist?

The newer tools seem pretty stable, with the apparent exception of the
schematic path. Perhaps they can be induced to work with EDIF input
generated from the old schematic flow.

(If so, that may open the way to finding other, non-Xilinx, schematic
tools capable of generating compatible EDIF. Altium may have something
worth looking at, but not needing schematics, I haven't properly looked
at their products.)

- Brian

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  #24 (permalink)  
Old 11-15-2007, 02:48 PM
Ray Andraka
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Posts: n/a
Default Re: FPGA for hobby use

Brian Drummond wrote:

> Is there any technology-independent way out of the Viewlogic/Dos
> software? Such as a fairly generic EDIF netlist?


Yes, Viewlogic can output an edif netlist, at least it did some 10 years
ago when I last used it.


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  #25 (permalink)  
Old 11-15-2007, 10:21 PM
Andy
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Posts: n/a
Default Re: FPGA for hobby use

On Nov 15, 2:41 am, Herbert Kleebauer <[email protected]> wrote:
> - The essential drawback is the missing back annotation of the simulation
> results into the schematic. This is like debugging software with print
> statements instead of a source code debugger. A few years ago I tested
> an older version (I think it was ISI 2.1) and there at least you could
> attach probes in the schematic to display the states of signals.
> This also was only a makeshift, but better than nothing.


Now that's funny! You don't like HDL, but a source level (text)
debugger is a better idea?

Just how do you do a simulation without some sort of textual
stimulation (or with an hdl, at least you can have behavioral
stimulation)? Please don't tell me you click on a wire and start
typing ones and zeroes?

I think the bottom line is that graphics show structure better, text
shows behavior better. I use RTL viewers (synplicity and quartus are
really good) to extract the structural graphics from my HDL source if/
when I need it (presentations, reviews, etc.) It is a lot easier to do
that than to specify (or debug) behavior from graphics.

I'm old enough have done a lot of ABEL/CUPL for PALs, and schematic
capture for xc2000/xc3000 designs, and I hated VHDL for a long time.
My old boss hung up a quote of mine about trying to design SW by
drawing pictures, while HW design was hell-bent-for-leather, headed
the other way. Previous poster notwithstanding, I used GED (precursor
to Concept) to build wonderful, intelligently parameterizable
functional blocks that could be interconnected in an easily
understood, structual way. Unless I needed to design a state
machine... That's when I started to design behaviorally, instead of
structurally. Now, design structure is mostly about managing
behavioral complexity, and a only little about managing physical
complexity. Once you make that thought shift, it's gravy from there
on.

So where is the future of "schematic capture"? Just like in board
level design, when you are designing structurally with pre-
manufactured blocks, and just hooking them up with wires, that's where
graphical design entry makes sense. We're probably headed back there
with FPGA's, what with increased use of IP, where the bulk of our
"design" is hooking up pre-designed blocks of circuitry. So we dive
into a custom block every now and then to use HDL to design a custom
behavioral translator to make block A talk to block B...

BTW, I've used Concept and Capture (Orcad) for board design, and trust
me, Concept is WAY ahead of Capture. They keep adding features from
Concept into Capture though, so one of these days...

Alright, I've ambled on enough.

Andy
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