FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 02-23-2005, 03:54 PM
santhosh
Guest
 
Posts: n/a
Default FPGA : file generation

Getting unwanted zeroes generated in the coe file....Any one guess what can be the reason?
Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Icarus Verilog - bad VCD file generation [email protected] Verilog 2 09-29-2008 03:05 AM
VCD file generation sunil FPGA 5 04-23-2004 06:31 AM
Q: Xilinx PROM file generation Gerald Weile FPGA 1 09-05-2003 05:07 PM


All times are GMT +1. The time now is 09:52 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2021, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved