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11-14-2003, 05:22 AM

Sudip Saha

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FPGA Device Utilization

Hi All,

I am looking for documentation on
estimation of FPGA device utilization from a high level design specification(idea). Can anybody tell me where I can find out this kind of document which gives idea about how to do rough estimate of gate count(ASIC) or device utilization from a high level design description. The design will ofcourse be made in VHDL/Verilog.

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