FPGA board checking

Hello,

I am developing a FPGAs (BGA case) board.

Is it possible to check the connections between two pins on two
different FPGAs with the Boundary scan?

If so, exists there a tool that is able to make this kind of test using
the board schematic?

Thank you in advance.

smu

"smu" <[email protected]> wrote in message
news:[email protected]...
> Hello,
>
> I am developing a FPGAs (BGA case) board.
>
> Is it possible to check the connections between two pins on two
> different FPGAs with the Boundary scan?
>
> If so, exists there a tool that is able to make this kind of test using
> the board schematic?
>
> Thank you in advance.
>
> smu

yes, checking connections is defenetly possible. Also many other things,
like programming non JTAG memories and other non JTAG devices if those are
connected to FPGAs or devices with JTAG boundary scan.

check out
www.jtag,com

I guess pretty much expensive tools.

if you dont mind some programming yourself I have an windows application
that uses 2 PLDs in JTAG chain to program an FPGA (not on boundary scan!)
and then via that FPGA an parallel Flash memory. This application could be
modified to test your custom board. The schematics extraction would be
manual, or if you can import netlist from sch a netlist reader could be
added to provide the link to your schematics.

Antti

smu wrote:
>
> Hello,
>
> I am developing a FPGAs (BGA case) board.
>
> Is it possible to check the connections between two pins on two
> different FPGAs with the Boundary scan?
>
> If so, exists there a tool that is able to make this kind of test using
> the board schematic?

I recall that Memec was selling a low cost boundary scan tester just for
this sort of thing. I don't remember what it was called, or what it
cost, but I do remember that "low cost" was getting more expensive. I
guess they found that they had to raise prices to make ends meet. This
tends to be a low volume business area and so they have to charge higher
prices. Too bad there are no open source tools for this. But I have
not even found much support from the chip makers in this area. They
build boundary scan into their chips and leave the rest to you! The
best you can hope for is a BSDL file.

--

Rick "rickman" Collins

[email protected]
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX

"smu" <[email protected]> wrote in message
news:[email protected]...
> Hello,
>
> I am developing a FPGAs (BGA case) board.
>
> Is it possible to check the connections between two pins on two
> different FPGAs with the Boundary scan?

If you have multiple pins between the two devices don't forget you
can write test designs to pass data back and forward to and
from each device multiple times.

If you have detectors on each input pin you might be able to
read back the status of each, this spotting where any
errors are occurring.


Nial

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone Based 'Easy PCI' proto board
www.nialstewartdevelopments.co.uk

smu <[email protected]> wrote in message news:<[email protected]>...
> Hello,
>
> I am developing a FPGAs (BGA case) board.
>
> Is it possible to check the connections between two pins on two
> different FPGAs with the Boundary scan?
>
> If so, exists there a tool that is able to make this kind of test using
> the board schematic?
>
> Thank you in advance.
>
> smu

Intel has an apnote on using jtag scanning with the 386ex. Includes a
dos driver and schematic - hw attaches to parallel printer port.

You can try with universalscan software

>"smu" <[email protected]> wrote in message
>news:[email protected]...
>> Hello,
>>
>> I am developing a FPGAs (BGA case) board.
>>
>> Is it possible to check the connections between two pins on two
>> different FPGAs with the Boundary scan?
>>
>> If so, exists there a tool that is able to make this kind of tes
using
>> the board schematic?
>>
>> Thank you in advance.
>>
>> smu
>
>yes, checking connections is defenetly possible. Also many other things,
>like programming non JTAG memories and other non JTAG devices if thos
are
>connected to FPGAs or devices with JTAG boundary scan.
>
>check out
>www.jtag,com
>
>I guess pretty much expensive tools.
>
>if you dont mind some programming yourself I have an windows application
>that uses 2 PLDs in JTAG chain to program an FPGA (not on boundar
scan!)
>and then via that FPGA an parallel Flash memory. This application coul
be
>modified to test your custom board. The schematics extraction would be
>manual, or if you can import netlist from sch a netlist reader could be
>added to provide the link to your schematics.
>
>Antti
>
>
>