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  #1 (permalink)  
Old 10-07-2005, 02:02 AM
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Default FPGA behaviour when its used resource is >90% ?

Hi,
We are using Xilinx Spartan2E in our platform and so far functioning of
every logical cores was looking good. Today, I saw some weird behaviour
after addng additional logic, all of sudden I was missing some signals
coming out of FPGA and some signals looks different. This additional
logic does not interfer with the exisitng logic cores.
I am reaching upper limit of FPGA resource but still I can fit in all
the logic cores.

So my question is, by utilizing the FPGA resource around 90%, does the
behaviour of FPGA logics becomes unpredictible ?

Any pointers or suggestions in this regard is much appreciated.

Thank you in advance.

-Kiran

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  #2 (permalink)  
Old 10-07-2005, 08:05 AM
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Default Re: FPGA behaviour when its used resource is >90% ?


> I am reaching upper limit of FPGA resource but still I can fit in all
> the logic cores.


Is the timing analysis still good ?

Rgds
André

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  #3 (permalink)  
Old 10-07-2005, 08:13 AM
Antti Lukats
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Default Re: FPGA behaviour when its used resource is >90% ?

<[email protected]> schrieb im Newsbeitrag
news:[email protected] oups.com...
> Hi,
> We are using Xilinx Spartan2E in our platform and so far functioning of
> every logical cores was looking good. Today, I saw some weird behaviour
> after addng additional logic, all of sudden I was missing some signals
> coming out of FPGA and some signals looks different. This additional
> logic does not interfer with the exisitng logic cores.
> I am reaching upper limit of FPGA resource but still I can fit in all
> the logic cores.
>
> So my question is, by utilizing the FPGA resource around 90%, does the
> behaviour of FPGA logics becomes unpredictible ?
>
> Any pointers or suggestions in this regard is much appreciated.
>
> Thank you in advance.
>
> -Kiran
>


the logic utilization numer is somewhat magic/bogus, but reaching the limit
makes the probability of unexplained behaviour larger, yes.

at the very basics a rock solid design should work. should work no matter
what, if it runs the toolflow it should work (no matter the utilization).
but its hardly ever so in real life. so adding unrelated logic (even when
total utilization is not nearly at the max) may introduce unexpected
failures.

there is no direct advice for you, lots of troubleshooting may be required.
the extra logic may iterfere to the way the rest of the logic can be placed
what makes the timing different and that can cause problems that did happen
before

Antti







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  #4 (permalink)  
Old 10-07-2005, 08:32 AM
Zara
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Default Re: FPGA behaviour when its used resource is >90% ?

On 6 Oct 2005 18:02:25 -0700, [email protected] wrote:

>Hi,
>We are using Xilinx Spartan2E in our platform and so far functioning of
>every logical cores was looking good. Today, I saw some weird behaviour
>after addng additional logic, all of sudden I was missing some signals
>coming out of FPGA and some signals looks different. This additional
>logic does not interfer with the exisitng logic cores.
>I am reaching upper limit of FPGA resource but still I can fit in all
>the logic cores.
>
>So my question is, by utilizing the FPGA resource around 90%, does the
>behaviour of FPGA logics becomes unpredictible ?
>
>Any pointers or suggestions in this regard is much appreciated.
>
>Thank you in advance.
>
>-Kiran


Look at possible timing constraints violation. If neccessary, make
constraints stricter, by increasing the frequency and/or adding jitter
to the clocks

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  #5 (permalink)  
Old 10-07-2005, 02:02 PM
Aurelian Lazarut
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Default Re: FPGA behaviour when its used resource is >90% ?

Kiran,
please send me some design files that you can share, and I'll take a look

Aurash

[email protected] wrote:

>Hi,
>We are using Xilinx Spartan2E in our platform and so far functioning of
>every logical cores was looking good. Today, I saw some weird behaviour
>after addng additional logic, all of sudden I was missing some signals
>coming out of FPGA and some signals looks different. This additional
>logic does not interfer with the exisitng logic cores.
>I am reaching upper limit of FPGA resource but still I can fit in all
>the logic cores.
>
>So my question is, by utilizing the FPGA resource around 90%, does the
>behaviour of FPGA logics becomes unpredictible ?
>
>Any pointers or suggestions in this regard is much appreciated.
>
>Thank you in advance.
>
>-Kiran
>
>
>



--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/

phone: 353 01 4032639
fax: 353 01 4640324


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  #6 (permalink)  
Old 10-07-2005, 03:25 PM
Mike Harrison
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Posts: n/a
Default Re: FPGA behaviour when its used resource is >90% ?

On Fri, 07 Oct 2005 14:02:27 +0100, Aurelian Lazarut <[email protected]> wrote:

>Kiran,
>please send me some design files that you can share, and I'll take a look
>
>Aurash
>
>[email protected] wrote:
>
>>Hi,
>>We are using Xilinx Spartan2E in our platform and so far functioning of
>>every logical cores was looking good. Today, I saw some weird behaviour
>>after addng additional logic, all of sudden I was missing some signals
>>coming out of FPGA and some signals looks different. This additional
>>logic does not interfer with the exisitng logic cores.
>>I am reaching upper limit of FPGA resource but still I can fit in all
>>the logic cores.
>>
>>So my question is, by utilizing the FPGA resource around 90%, does the
>>behaviour of FPGA logics becomes unpredictible ?
>>
>>Any pointers or suggestions in this regard is much appreciated.
>>
>>Thank you in advance.
>>
>>-Kiran


The addition of the new logic may have caused increased routing delays.
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  #7 (permalink)  
Old 10-10-2005, 04:28 AM
bijoy
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Default Re: FPGA behaviour when its used resource is >90% ?

Hi Antii

How can i identify the unrelated logic ? what is the meaning of unrelated logic. ?

could you please explain about it ?

regards bijoy
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  #8 (permalink)  
Old 10-10-2005, 08:46 AM
Nial Stewart
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Default Re: FPGA behaviour when its used resource is >90% ?

> So my question is, by utilizing the FPGA resource around 90%, does the
> behaviour of FPGA logics becomes unpredictible ?
> Any pointers or suggestions in this regard is much appreciated.
> Thank you in advance.
> -Kiran




If your design is _properly_ constrained, and if the timing analysis after
a build says everything's OK, then the amount of logic in the device shouldn't
have any effect on the performance.


Nial.


-------------------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk


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  #9 (permalink)  
Old 10-10-2005, 08:55 AM
Simon Peacock
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Default Re: FPGA behaviour when its used resource is >90% ?

unrelated logic means just what it says .. unrelated.. that means logic
which doesn't have an interconnect. It might even be from different parts
of the design. The only thing they have in common is they have nothing to
do with each other. A bit like reality TV but without the camera :-)

Simon


"bijoy" <[email protected]> wrote in message
news:[email protected]
> Hi Antii
>
> How can i identify the unrelated logic ? what is the meaning of unrelated

logic. ?
>
> could you please explain about it ?
>
> regards bijoy



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