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Old 11-01-2007, 08:42 PM
fazulu deen
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Default fpga based designs

Dear all,

Is it possible to implement power management unit(idle and active) in
FPGA?

pls give suggestions to implement clock generation unit in FPGA....

regards,
fazal

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  #2 (permalink)  
Old 11-01-2007, 10:07 PM
John_H
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Default Re: fpga based designs

"fazulu deen" <[email protected]> wrote in message
news:[email protected] ps.com...
> Dear all,
>
> Is it possible to implement power management unit(idle and active) in
> FPGA?
>
> pls give suggestions to implement clock generation unit in FPGA....
>
> regards,
> fazal


Is it possible to ask the question in a way that we can answer?

Are you trying to control the FPGA from the FPGA? Control a procesor from
the FPGA? Control a nuclear power pland from the FPGA? What kind of clock
generation are you looking for?

Please think about the kind of answer you want and ask the question in a way
that's obvious what you're driving toward.

Please.

- John_H


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  #3 (permalink)  
Old 11-01-2007, 10:08 PM
John McCaskill
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Default Re: fpga based designs

On Nov 1, 1:42 pm, fazulu deen <[email protected]> wrote:
> Dear all,
>
> Is it possible to implement power management unit(idle and active) in
> FPGA?
>
> pls give suggestions to implement clock generation unit in FPGA....
>
> regards,
> fazal



If you mean can you reduce the power in the FPGA when it is idle by
adjusting the clock, yes. For Xilinx FPGAs, there is the BUFGMUX that
will let you switch between two clock sources glitch free. If you
have a fast clock for when the FPGA is active, and a slow clock for
when it is idle, you can switch between them.

Give some more details about what you need to do, and you might get
some more help. But make sure you convince everyone it is not a
homework problem first

Regards,

John McCaskill
www.fastertechnology.com

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  #4 (permalink)  
Old 11-04-2007, 10:38 AM
vasile
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Default Re: fpga based designs

On Nov 1, 1:08 pm, John McCaskill <[email protected]> wrote:
> On Nov 1, 1:42 pm, fazulu deen <[email protected]> wrote:
>
> > Dear all,

>
> > Is it possible to implement power management unit(idle and active) in
> > FPGA?

>
> > pls give suggestions to implement clock generation unit in FPGA....

>
> > regards,
> > fazal

>
> If you mean can you reduce the power in the FPGA when it is idle by
> adjusting the clock, yes.


If you mean if you can reduce the power in the FPGA turning OFF unused
banks, the answer is no.
There are a lot of Xilinx and Altera engineers on this list. Just for
them: as long many DSP's and SDRAMs have power management units
allowing partial refresh, partial power supply etc, why this feature
is not implemented in the FPGA ?

thx,
Vasile

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  #5 (permalink)  
Old 11-14-2007, 11:19 PM
Kris Vorwerk
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Default Re: fpga based designs

> Is it possible to implement power management unit(idle and active) in
> FPGA?


Just as a follow-up on what some others have mentioned in this
thread .... Actel's Igloo FPGAs come with a pin which allow the FPGA
to (effectively) power-down for idle periods. (Actel refers to this
as "Flash*Freeze".) Similarly, and as mentioned elsewhere in this
thread, these devices contain glitchless muxes (the NGMUX macro) which
allows you to switch between high-and-low-speed clocks for power
management.


K.

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