FPGA Central

Hello all,

I have a question regarding migration of design from Xilinx FPGA to
ASIC. There are lot of Xilinx IP Cores(I am sure even Altera will have
too) which are commonly used for Arithmetic Purposes. For instance my
design uses the Xilinx FFT/IFFT IP Cores and if the design has to be
moved to the ASIC at later stages, can Xilinx Provide the netlist for
ASIC technology as well?

I hope I put down my query clearly and will be glad to receive
responses.

Thanks in advance,

Venkat.

Venkat wrote:
> Hello all,
>
> I have a question regarding migration of design from Xilinx FPGA to
> ASIC. There are lot of Xilinx IP Cores(I am sure even Altera will have
> too) which are commonly used for Arithmetic Purposes. For instance my
> design uses the Xilinx FFT/IFFT IP Cores and if the design has to be
> moved to the ASIC at later stages, can Xilinx Provide the netlist for
> ASIC technology as well?
>
> I hope I put down my query clearly and will be glad to receive
> responses.
>

This isn't answering your question, but I personally have very good
experience with the Altera HardCopy FPGA to ASIC migration program. It
allows you to have an ASIC which is pin compatible, using the same
drivers etc, all out of a single toolchain. We used it at a former
employer of mine.

-hpa

On Mon, 8 Dec 2008 16:50:08 -0800 (PST), Venkat
<[email protected]> wrote:

>Hello all,
>
>I have a question regarding migration of design from Xilinx FPGA to
>ASIC. There are lot of Xilinx IP Cores(I am sure even Altera will have
>too) which are commonly used for Arithmetic Purposes. For instance my
>design uses the Xilinx FFT/IFFT IP Cores and if the design has to be
>moved to the ASIC at later stages, can Xilinx Provide the netlist for
>ASIC technology as well?

Xilinx very clearly states that any IP they give you is for their
devices only. I'm not sure what their policy is for licensing source
of their IP for ASIC porting. Obviously they can provide the source
but whether they do is another question. You may have to find other
sources to replace the IP blocks you used when you need to do ASIC
porting.

Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services
http://www.dspia.com

Venkat wrote:
> I have a question regarding migration of design from Xilinx FPGA to
> ASIC. There are lot of Xilinx IP Cores(I am sure even Altera will have
> too) which are commonly used for Arithmetic Purposes. For instance my
> design uses the Xilinx FFT/IFFT IP Cores and if the design has to be
> moved to the ASIC at later stages, can Xilinx Provide the netlist for
> ASIC technology as well?

The only sane way to design is to use 3rd party IP that can be ported
to ASIC or design the IP yourself. Xilinx will not give you the IP
for ASIC porting. It might not be even very suitable for that because
it is partly full custom hard IP partly soft IP. Maybe if you have deep
enough pockets and big enough company behind you might get some deal,
but I wouldn't count on it.

If the FPGA is only a prototyping vechile before ASIC, the design should
be done for the ASIC and ported to FPGA. The FPGA port will be
suboptimal, it might require a big FPGA, low clock frequency etc. but
can be used for prototyping.

Vendor specific IP cores are a way to force the user to use one FPGA
architecture, and also force to it in the future if the designs are
updated etc.

--Kim

Kim Enkovaara wrote:

> Vendor specific IP cores are a way to force the user to use one FPGA
> architecture, and also force to it in the future if the designs are
> updated etc.

I agree. Using a device specific core,
or even a primitive, is a gamble.
My best odds to keep control of a design
for verification, maintenance
and portability, is to own the source code.

-- Mike Treseler