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Old 09-03-2004, 02:03 PM
Ted
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Default Fanout Xilinx

Hello All,

I am trying to obtain the total fanout of all nets in my design. I
tried using timing to do it and yes, I have all the fanouts. However,
there seems to be number of problems:

1) Path overlaps indicating that the same net might be used more than
the total number of fanouts indicated.

2) What are Tiopi, Tilo and Tioop? Are they different type of wires?
Where is documentation for these things? I can't seem to find them in
the help files.

Is there any straight forward way of finding total fanout besides
parsing the output file with perl or something? Thanks.

Ted
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Old 09-03-2004, 07:44 PM
Jim Wu
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Default Re: Fanout Xilinx

>
> 2) What are Tiopi, Tilo and Tioop? Are they different type of wires?
> Where is documentation for these things? I can't seem to find them in
> the help files.


They are different timing parameters. If you have ISE installed, check
doc\usenglish\help\timingan\html directory for descriptions about them.
(e.g. for Tioipi, search for file ta_tiopi.htm)

HTH,
Jim ([email protected] remove NOOOSPAM)
http://www.geocities.com/jimwu88/chips
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