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Old 11-16-2004, 09:25 AM
Jac Athow
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Default Extending chipscope capture memory by using external async SRAM

Im just beginning to read about Chipscope from Xilinx, and up to now,
Im impressed by the product, and how easy it is to use. But the
obvious question that comes to my mind is that...

Is this doable; to extend the capture mem of ICON by connecting it
somehow to external async SRAM. For our purpose (~5MHZ clk), which is
slow by BRAM standard, it would be just a waste to spend all the bram
of my XCV300 on the ILA. I think it is actually feasible,
disconnecting the busses going to the BRAM, maybe using FPGA editor,
from the ICON core and reroute them to external ram, but without
proper documentation, this might take a while.

Has anyone done something like that?

Regards
Jac
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Old 11-18-2004, 08:55 PM
Antti Lukats
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Default Re: Extending chipscope capture memory by using external async SRAM

"Jac Athow" <[email protected]> wrote in message
news:[email protected] om...
> Im just beginning to read about Chipscope from Xilinx, and up to now,
> Im impressed by the product, and how easy it is to use. But the
> obvious question that comes to my mind is that...
>
> Is this doable; to extend the capture mem of ICON by connecting it
> somehow to external async SRAM. For our purpose (~5MHZ clk), which is
> slow by BRAM standard, it would be just a waste to spend all the bram
> of my XCV300 on the ILA. I think it is actually feasible,
> disconnecting the busses going to the BRAM, maybe using FPGA editor,
> from the ICON core and reroute them to external ram, but without
> proper documentation, this might take a while.
>
> Has anyone done something like that?


the closest we have done are
1) connecting a custom VIO like core to ICON
2) connecting a custom core to ICON allowing the ICON to be used to download
brams blocks
3) collecting data from ILA using custom Analyzer style application

what you want todo, is not directly doable.
ICON is basically a JTAG HUB, it allows up to 15 cores to be "inserted" into
the JTAG chain (using the xilinx BSCAN primitive)

the actual "work" is done inside the cores connected to ICON, in most of the
cases the ILA core, in order to use external RAM you would need to write
your own "ICON compatible" ILA core

Antti


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