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Old 04-20-2006, 07:37 PM
Weng Tianxiang
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Default An experience with Xilinx 8.1.02i

Hi,
I would like to share with you my an experience with error generation
when inconsistant Xilinx Navigator 8.1.02i settings were made.

1. My project has two Virtex II-1500 chips in a design. The code for
both chips were compiled correctly with version 7.1.4i.

2. It is the first time to compile with 8.1.02i.

3. Chip A design was successfully compiled.

4. Chip B design generated 34 errors due to trimming of some key
signals.

Those signals couldn't be trimmed for a correct design.

After efforts of several hours were made, I finally identified the
error reason:
Inconsistant parameter settings caused the errors and unnecessary
trimming.

1. For synthesis property/synthesis options:
"Keep Hierachy", "No" is selected

2. For "Implement Design"/Property/Translate Property
"Preserve Hierachy on Sub Module", Yes is selected.

When compiling, signals beloging to interface between sub module and
main module were trimmed and 34 Map errors were generated.

The following are two error information:
ERROR:MapLib:661 - LUT4 symbol "_n218330" (output signal=nREQ64_O_On)
has input
signal "nREQ64Pass_SDRAM<0>" which will be trimmed. See the trim
report for
details about why the input signal will become undriven.
ERROR:MapLib:661 - LUT4 symbol "M_T_StateA/_n000919" (output
signal=M_T_StateA/_n0009) has input signal "nREQ_O_R" which will be
trimmed.
See the trim report for details about why the input signal will
become
undriven.

After no is selected with selection "Preserve Hierachy on Sub Module",
compilation went smoothly and successfully.

I think further Xilinx versions should prohibit second option to be
selected when first one is selected to prevent similar error situations
from happening.

Weng

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