Error in Verilog Code
hi
module test_readmemory(
);
reg [0:7] mem [1:30];
initial
$readmemb("memory.mem",mem);
always @(mem)
$display("mems= %b,%b,%h,%h", mem[1],mem[10],mem[15],mem[30]);
endmodule
The file memory.mem contains these data
209
210
211
211
212
212
212
211
211
212
213
213
213
213
213
212
213
213
213
213
212
213
212
212
212
213
212
211
211
211 While simulating this design in xilinx ise, some times I am
getting error "ERROR:Simulator - Failed to link the design. Check to
see if any previous simulation executables are still running."
what is this error. how to eliminate it.
and sometimes I am getting outputs 8'h09, 8'h12, 8'h13, 8'h11
In the input file, mem[1] = 209 but output i am getting is 8'h09
mem[10]=212 but output iam getting is 8'12
similarly mem[15] and mem[30].
8 binary numbers are sufficient to represent upto 256. But, why I am
getting like this??
Please let me know asap
thanks
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