FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 10-17-2003, 12:40 PM
Vazquez
Guest
 
Posts: n/a
Default Error Message when using process with wait-statement in testbench

Dear Sir or Madame,

when I try to compile a testbench including the following process
I get the following error message:
"Error: VHDL Wait Statement error at tb_reservoir_positions.vhd(55):
Wait Statement must contain condition clause with UNTIL keyword."


process
begin
t_reset <= '1', '0' after 100 ns;
wait;
end process;

I thought that is was a legal wait-statement when writing a testbench for functional
simulation.
So what could be the reason for that error message?
(p.s. I am using the Quartus II WebEdition 3.0)

Kind regards
Andrés Vázquez
G&D System Development
Reply With Quote
  #2 (permalink)  
Old 10-17-2003, 06:32 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: Error Message when using process with wait-statement in testbench

Vazquez wrote:

> process
> begin
> t_reset <= '1', '0' after 100 ns;
> wait;
> end process;
>
> I thought that is was a legal wait-statement when writing a testbench for functional
> simulation.


The problem is that the wait is unconditional.
Even if the code were legal, you would never
get past the first loop of the process at 0 nS.

-- Mike Treseler

Reply With Quote
  #3 (permalink)  
Old 10-20-2003, 10:10 AM
Vazquez
Guest
 
Posts: n/a
Default Re: Error Message when using process with wait-statement in testbench

Hi,
so how can I write a process (within a testbench!) for a reset signal
which should be
asynchronous?

Best regards
Andrés Vázquez
G&D

Mike Treseler <[email protected]> wrote in message news:<[email protected]>...
> Vazquez wrote:
>
> > process
> > begin
> > t_reset <= '1', '0' after 100 ns;
> > wait;
> > end process;
> >
> > I thought that is was a legal wait-statement when writing a testbench for functional
> > simulation.

>
> The problem is that the wait is unconditional.
> Even if the code were legal, you would never
> get past the first loop of the process at 0 nS.
>
> -- Mike Treseler

Reply With Quote
Reply

Bookmarks

« VFDs | Virtex CLB »
Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Conditional wait statement in a verilog testbench kb33 Verilog 7 09-21-2007 07:49 PM
wait statement. [LinuxFc4]GaLaKtIkUs™ Verilog 13 08-25-2005 07:31 PM
What does this error message mean ? jg.lee Verilog 0 08-23-2005 10:44 PM
wait statement with Xilinx ise webpack4.2 Marco© Verilog 3 02-03-2004 09:34 AM


All times are GMT +1. The time now is 09:25 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved