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-   -   Error Message when using process with wait-statement in testbench (http://www.fpgacentral.com/group/showthread.php?t=50529)

Vazquez 10-17-2003 12:40 PM

Error Message when using process with wait-statement in testbench
 
Dear Sir or Madame,

when I try to compile a testbench including the following process
I get the following error message:
"Error: VHDL Wait Statement error at tb_reservoir_positions.vhd(55):
Wait Statement must contain condition clause with UNTIL keyword."


process
begin
t_reset <= '1', '0' after 100 ns;
wait;
end process;

I thought that is was a legal wait-statement when writing a testbench for functional
simulation.
So what could be the reason for that error message?
(p.s. I am using the Quartus II WebEdition 3.0)

Kind regards
Andrés Vázquez
G&D System Development

Mike Treseler 10-17-2003 06:32 PM

Re: Error Message when using process with wait-statement in testbench
 
Vazquez wrote:

> process
> begin
> t_reset <= '1', '0' after 100 ns;
> wait;
> end process;
>
> I thought that is was a legal wait-statement when writing a testbench for functional
> simulation.


The problem is that the wait is unconditional.
Even if the code were legal, you would never
get past the first loop of the process at 0 nS.

-- Mike Treseler


Vazquez 10-20-2003 10:10 AM

Re: Error Message when using process with wait-statement in testbench
 
Hi,
so how can I write a process (within a testbench!) for a reset signal
which should be
asynchronous?

Best regards
Andrés Vázquez
G&D

Mike Treseler <[email protected]> wrote in message news:<[email protected]>...
> Vazquez wrote:
>
> > process
> > begin
> > t_reset <= '1', '0' after 100 ns;
> > wait;
> > end process;
> >
> > I thought that is was a legal wait-statement when writing a testbench for functional
> > simulation.

>
> The problem is that the wait is unconditional.
> Even if the code were legal, you would never
> get past the first loop of the process at 0 nS.
>
> -- Mike Treseler



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