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  #1 (permalink)  
Old 06-10-2009, 07:55 PM
Pablo
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Default Error in FSL Bus


I receive this message when I build "Software Applications".

I am not sure but I think that hardware is not right although I don't
receive any error message when I build the Bitstream.

/cygdrive/c/Windows/Temp//ccDJflt9.s: Assembler messages:
/cygdrive/c/Windows/Temp//ccDJflt9.s:72: Error: register expected, but
saw 'rfsli'
/cygdrive/c/Windows/Temp//ccDJflt9.s:72: Warning: ignoring operands:
rfsli
make: *** [mb0_thread/executable.elf] Error 1
Done!


my best regards
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  #2 (permalink)  
Old 06-11-2009, 08:13 AM
Goran_Bilski
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Default Re: Error in FSL Bus

On Jun 10, 7:55*pm, Pablo <[email protected]> wrote:
> I receive this message when I build "Software Applications".
>
> I am not sure but I think that hardware is not right although I don't
> receive any error message when I build the Bitstream.
>
> /cygdrive/c/Windows/Temp//ccDJflt9.s: Assembler messages:
> /cygdrive/c/Windows/Temp//ccDJflt9.s:72: Error: register expected, but
> saw 'rfsli'
> /cygdrive/c/Windows/Temp//ccDJflt9.s:72: Warning: ignoring operands:
> rfsli
> make: *** [mb0_thread/executable.elf] Error 1
> Done!
>
> my best regards


Seems like you are using rfsli when it should be rfsl0 (or rather
rfsl<n> where n is the fsl channel.
Can you show the code section where you using the fsl interface?

Göran
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  #3 (permalink)  
Old 06-11-2009, 10:02 AM
Pablo
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Default Re: Error in FSL Bus

On 11 jun, 08:13, Goran_Bilski <[email protected]> wrote:
> On Jun 10, 7:55*pm, Pablo <[email protected]> wrote:
>
> > I receive this message when I build "Software Applications".

>
> > I am not sure but I think that hardware is not right although I don't
> > receive any error message when I build the Bitstream.

>
> > /cygdrive/c/Windows/Temp//ccDJflt9.s: Assembler messages:
> > /cygdrive/c/Windows/Temp//ccDJflt9.s:72: Error: register expected, but
> > saw 'rfsli'
> > /cygdrive/c/Windows/Temp//ccDJflt9.s:72: Warning: ignoring operands:
> > rfsli
> > make: *** [mb0_thread/executable.elf] Error 1
> > Done!

>
> > my best regards

>
> Seems like you are using rfsli when it should be rfsl0 (or rather
> rfsl<n> where n is the fsl channel.
> Can you show the code section where you using the fsl interface?
>
> Göran


This is my system.mhs section:

BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 7.10.d
PARAMETER C_INSTANCE = microblaze_0
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER C_FSL_LINKS = 4
BUS_INTERFACE DPLB = mb_plb_0
BUS_INTERFACE IPLB = mb_plb_0
BUS_INTERFACE DEBUG = debug_module_MBDEBUG_0
BUS_INTERFACE DLMB = dlmb_0
BUS_INTERFACE ILMB = ilmb_0
BUS_INTERFACE SFSL0 = fsl_v20_0
BUS_INTERFACE MFSL0 = fsl_v20_1
BUS_INTERFACE SFSL1 = fsl_v20_2
BUS_INTERFACE MFSL1 = fsl_v20_3
BUS_INTERFACE SFSL2 = fsl_v20_4
BUS_INTERFACE MFSL2 = fsl_v20_5
BUS_INTERFACE SFSL3 = fsl_v20_0_mb0 *
Microblaze works as slave (ONLY)
PORT MB_RESET = mb_reset
PORT Interrupt = Interrupt
END


Azq_reg is the custom peripheral connected by FSL Bus
BEGIN azq_reg
PARAMETER INSTANCE = azq_reg_0
PARAMETER HW_VER = 1.00.a
PARAMETER Value = 0x00000000
BUS_INTERFACE MFSL = fsl_v20_0_mb0
END


The FSL Bus
BEGIN fsl_v20
PARAMETER INSTANCE = fsl_v20_0_mb0
PARAMETER HW_VER = 2.11.a
PARAMETER C_EXT_RESET_HIGH = 0
PORT FSL_Clk = sys_clk_s
PORT SYS_Rst = net_gnd
END


And the Azq_Reg.vhd:

------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity azq_reg is
generic
(
Value: in std_logic_vector(31 downto 0) :=
"00000000000000000000000000000010"
);
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
FSL_Clk : in std_logic;
FSL_Rst : in std_logic;
FSL_S_Clk : out std_logic;
FSL_S_Read : out std_logic;
FSL_S_Data : in std_logic_vector(0 to 31);
FSL_S_Control : in std_logic;
FSL_S_Exists : in std_logic;
FSL_M_Clk : out std_logic;
FSL_M_Write : out std_logic;
FSL_M_Data : out std_logic_vector(0 to 31);
FSL_M_Control : out std_logic;
FSL_M_Full : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);

attribute SIGIS : string;
attribute SIGIS of FSL_Clk : signal is "Clk";
attribute SIGIS of FSL_S_Clk : signal is "Clk";
attribute SIGIS of FSL_M_Clk : signal is "Clk";

end azq_reg;


architecture EXAMPLE of azq_reg is

-- Total number of input data.
constant NUMBER_OF_INPUT_WORDS : natural := 8;

-- Total number of output data
constant NUMBER_OF_OUTPUT_WORDS : natural := 8;

type STATE_TYPE is (Idle, Read_Inputs, Write_Outputs);

signal state : STATE_TYPE;

-- Accumulator to hold sum of inputs read at any point in time
signal sum : std_logic_vector(0 to 31);

-- Counters to store the number inputs read & outputs written
signal nr_of_reads : natural range 0 to NUMBER_OF_INPUT_WORDS - 1;
signal nr_of_writes : natural range 0 to NUMBER_OF_OUTPUT_WORDS -
1;

begin
FSL_S_Read <= FSL_S_Exists when state = Read_Inputs else '0';
FSL_M_Write <= not FSL_M_Full when state = Write_Outputs else '1';

FSL_M_Data <=
Value;
*** I use this peripheral to identify the microblaze processor.

......
......


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  #4 (permalink)  
Old 06-12-2009, 09:38 AM
Goran_Bilski
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Posts: n/a
Default Re: Error in FSL Bus

Hi,

Since you got an assembler error, I was more thinking of your
assembler code than your hardware implementation.

Göran
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