FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-16-2004, 08:50 AM
Kelvin @ SG
Guest
 
Posts: n/a
Default Error in Assembly stage.

Hi, there:

I could get all my three modules placed and routed, now how do I fix this
error? There is one thing strange, the
"Rejected due to connectivity: 1 out of 3361", what is causing
the connectivity to be changed?


Best Regards,
Kelvin




ERROR:Place - The following 1 components are required to be placed in a
specific
relative placement form. The required relative coordinates in the RPM
grid
(that can be seen in the FPGA-editor) are shown in brackets next to the
component names. Due to placement constraints it is impossible to place
the
components in the required form. SLICE
partial_digital_if/u_dataslicer/int_rst_2 (0, 0)
Constrained by statement: COMPGRP "PARTIAL.SLICE" LOCATE = SITE
"SLICE_X20Y191:SLICE_X175Y0" LEVEL 4 ;



Finished Guide File Processing.

Xilinx Place and Route Guide Results File
=========================================

Guide Summary Report:

Design Totals:
Components:
Name matched: 3361 out of 3540 94%
Rejected due to connectivity: 1 out of 3361
Total guided: 3360 out of 3361 99%

Signals:
Rejected Implicit/Internal: 3686 out of 10802
Name matched: 7111 out of 7116 99%
Total guided: 7101 out of 7111 99%
Total connections guided: 2558



Guide file: "../../pims/partial_digital_if/partial_digital_if.ncd"
Guide
mode: "exact"

Components:
Name matched: 3346 out of 3540 94%
Rejected due to connectivity: 1 out of 3346
Total guided: 3345 out of 3346 99%

Signals:
Name matched: 7099 out of 10802 65%
Total guided: 7068 out of 7099 99%
Total connections guided: 2457


Guide file: "../../pims/switch_qpsk/switch_qpsk.ncd" Guide mode:
"exact"

Components:
Name matched: 15 out of 3540 0%
Total guided: 15 out of 15 100%

Signals:
Name matched: 183 out of 10802 1%
Total guided: 481 out of 183 262%
Total connections guided: 101


For a detailed guide report refer to the "digital_if.grf" file.

Device utilization summary:

Number of External IOBs 101 out of 684 14%
Number of LOCed External IOBs 101 out of 101 100%

Number of SLICEs 3061 out of 33792 9%

Number of BUFGMUXs 11 out of 16 68%
Number of TBUFs 64 out of 16896 1%
Number of VCCs 303 out of 9410 3%



Overall effort level (-ol): Standard (default)
Placer effort level (-pl): Standard (default)
Placer cost table entry (-t): 1
Router effort level (-rl): Standard (default)

Starting initial Timing Analysis. REAL time: 12 mins 29 secs
Finished initial Timing Analysis. REAL time: 13 mins 3 secs

WARNING:Par:276 - The signal bus1_bm_2/TNET(1) has no load
WARNING:Par:276 - The signal bus1_bm_2/TNET(0) has no load
WARNING:Par:276 - The signal bus1_bm_3/TNET(0) has no load
WARNING:Par:276 - The signal bm_r0/TNET(1) has no load
WARNING:Par:276 - The signal bm_r0/TNET(0) has no load

Phase 1.1

ERROR:Place - The following 1 components are required to be placed in a
specific
relative placement form. The required relative coordinates in the RPM
grid
(that can be seen in the FPGA-editor) are shown in brackets next to the
component names. Due to placement constraints it is impossible to place
the
components in the required form. SLICE
partial_digital_if/u_dataslicer/int_rst_2 (0, 0)
Constrained by statement: COMPGRP "PARTIAL.SLICE" LOCATE = SITE
"SLICE_X20Y191:SLICE_X175Y0" LEVEL 4 ;


ERROR:Place - The following 1 components are required to be placed in a
specific
relative placement form. The required relative coordinates in the RPM
grid
(that can be seen in the FPGA-editor) are shown in brackets next to the
component names. Due to placement constraints it is impossible to place
the
components in the required form. SLICE
partial_digital_if/u_dataslicer/_n0105 (0, 0)
Constrained by statement: COMPGRP "PARTIAL.SLICE" LOCATE = SITE
"SLICE_X20Y191:SLICE_X175Y0" LEVEL 4 ;

Phase 1.1 (Checksum:99478b) REAL time: 14 mins 5 secs


Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Simple way to implement multi-stage pipeline design in Verilog [email protected] Verilog 1 12-05-2008 07:50 PM
Low Cost High quality pcb prototype and Assembly manufacturer(CHINA) [email protected] Verilog 0 04-27-2006 07:41 AM
4-stage fixed-point binomial pipeline >>>>> urgent help dolly Verilog 5 11-09-2004 04:29 AM
Re: 4-stage fixed-point binomial pipeline >>>>> urgent help Prasanth Kumar Verilog 1 10-28-2004 02:15 PM


All times are GMT +1. The time now is 04:10 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved