FPGA Central

Hello:

I have mapped a design on Virtex2-6000 grade-4 device, and i would
like to emulate the design on ProDesign Platinum Edition Board.

PostLayout simulation of the design is working properly with the
testbench. i.e after Place and Route, backannotated the design and
static timing simulation is done. Results are matched after
postlayout. There are no timing errors after PAR. After configuring
the Platinum board with the '.bit' file (Configuration sw is supplied
by Prodesign), design is not visible to the PC. i.e. user Client
Application Modules (User CAPIMs) are not recognised by 'UMR Shell
script'. that means, emulated design is not visible. (Design size is
35%of Total FPGA)

In another case, with the some other test design (design size of <5%)
and with the same CAPIM, emulation software becomes visible to the PC
and CAPIMs are found by 'UMR shell script' and the design is also
perfectly functional.

Can any body suggest the ideas to solve the above problem? i.e does it
depend on size of design? and if yes, how? or any other solution

sateesh