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  #1 (permalink)  
Old 05-14-2009, 10:50 AM
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Default EMACS VHDL mode: how to rescan project so that makefile generatescorrectly?

Hi,
I'm using EMACS vhdl-mode to generate a makefile for simulation. My
problem is that I don't know how to tell EMACS to rescan the source
code folders before re-generating the makefile. If it doesn't rescan
then it doesn't find new files I have added or new dependencies. My
workaround is to close down emacs. Delete the emacs cache file. Reopen
emacs, and then regenerate the makefile.

Is there a simple way to force emacs to rescan the source code
folders?

Cheers
Andrew
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  #2 (permalink)  
Old 05-14-2009, 05:58 PM
Andy Botterill
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Default Re: EMACS VHDL mode: how to rescan project so that makefile generatescorrectly?

[email protected] wrote:
> Hi,
> I'm using EMACS vhdl-mode to generate a makefile for simulation. My
> problem is that I don't know how to tell EMACS to rescan the source
> code folders before re-generating the makefile. If it doesn't rescan
> then it doesn't find new files I have added or new dependencies. My
> workaround is to close down emacs. Delete the emacs cache file. Reopen
> emacs, and then regenerate the makefile.


Sorry I can't help you on this. Is there a verilog mode for emacs.
Highlighting would be good. Being able to match begin and end statements
would save me significant pain. Andy
>
> Is there a simple way to force emacs to rescan the source code
> folders?
>
> Cheers
> Andrew

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  #3 (permalink)  
Old 05-14-2009, 06:03 PM
phil hays
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Default Re: EMACS VHDL mode: how to rescan project so that makefilegenerates correctly?

Andy Botterill wrote:

> Is there a verilog mode for emacs.


http://www.verilog.com/verilog-mode.html

First hit from Googling verilog mode emacs


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  #4 (permalink)  
Old 05-14-2009, 07:25 PM
Andy Botterill
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Default Re: EMACS VHDL mode: how to rescan project so that makefile generatescorrectly?

phil hays wrote:
> Andy Botterill wrote:
>
>> Is there a verilog mode for emacs.

>
> http://www.verilog.com/verilog-mode.html
>
> First hit from Googling verilog mode emacs
>
>


I have already installed (from www.veripool.org) verilog-mode-494.el .
I do not see anything which allows me to relate a begin to a specific
end. If the www.verilog.com emacs mode does this I will install it. Does
it do this please. Thanks Andy
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  #5 (permalink)  
Old 05-14-2009, 08:11 PM
Mike Treseler
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Default Re: EMACS VHDL mode: how to rescan project so that makefile generatescorrectly?

[email protected] wrote:
> Hi,
> I'm using EMACS vhdl-mode to generate a makefile for simulation. My
> problem is that I don't know how to tell EMACS to rescan the source
> code folders before re-generating the makefile.


On the speedbar:
center-click project,
right-click and hold down, speedbar, rescan-project


-- Mike Treseler
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  #6 (permalink)  
Old 05-14-2009, 09:21 PM
Florian Stock
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Default Re: EMACS VHDL mode: how to rescan project so that makefile generates correctly?

Andy Botterill <[email protected]> writes:

> phil hays wrote:
>> Andy Botterill wrote:
>>
>>> Is there a verilog mode for emacs.

>>
>> http://www.verilog.com/verilog-mode.html
>>
>> First hit from Googling verilog mode emacs

>
> I have already installed (from www.veripool.org) verilog-mode-494.el .
> I do not see anything which allows me to relate a begin to a specific
> end. If the www.verilog.com emacs mode does this I will [...]


I have the one from Michael McNamara (www.verilog.com).
With ***p-moves you can move from begin to end and vice-versa (bound to
C-M-b and C-M-f).

Florian
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  #7 (permalink)  
Old 05-25-2009, 06:39 AM
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Default Re: EMACS VHDL mode: how to rescan project so that makefile generatescorrectly?

> On the speedbar:
> *center-click project,
> *right-click and hold down, speedbar, rescan-project


Thanks Mike, but I just don't see the rescan-project option.

Here is what I do:
open a .vhd file
vhdl menu, select speedbar to open up the speedbar window

When I right-click, hold down, speedbar: I don't see the rescan-
project option. I see a list of options starting with Update, Auto-
update, .... Customise, Close, Quit.

I don't quite understand your hint "center-click the project file".
vhdl menu export project creates a .prj file. But this file doesn't
show up in the speed bar? Is this the .prj file you are suggesting I
center-click in the speedbar?

Cheers
Andrew
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  #8 (permalink)  
Old 05-26-2009, 12:55 PM
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Default Re: EMACS VHDL mode: how to rescan project so that makefile generatescorrectly?


> Thanks Mike, but I just don't see the rescan-project option.
>
> Here is what I do:
> *open a .vhd file
> *vhdl menu, select speedbar to open up the speedbar window
>
> When I right-click, hold down, speedbar: I don't see the rescan-
> project option. I see a list of options starting with Update, Auto-
> update, .... Customise, Close, Quit.
>
> I don't quite understand your hint "center-click the project file".
> vhdl menu export project creates a .prj file. But this file doesn't
> show up in the speed bar? Is this the .prj file you are suggesting I
> center-click in the speedbar?
>
> Cheers
> Andrew


On my vhdl-mode speedbar (vhdl-mode 3.33.21/Emacs 21.3.1/win XP
environment)
it pops up as a menu entry #16 from top, it also says (R) as a hint on
which key to press.


I also have a make target "mf" to do this:
[I put all emacs project setup stuff in emacs.prj]

# Makefile syntax (note tabs, not spaces!!)
mf :
$(if $(wildcard emacs.prj), \
${RM} -rf .emacs-vhdl-cache-*; \
emacs -batch -l vhdl-mode -project <your_project_name> -f vhdl-
generate-makefile, \
$(error You must have an emacs.prj file))
# end Makefile

Regards -- Pontus
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  #9 (permalink)  
Old 05-27-2009, 12:27 AM
Mike Treseler
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Default Re: EMACS VHDL mode: how to rescan project so that makefile generatescorrectly?

[email protected] wrote:
>> On the speedbar:
>> center-click project,
>> right-click and hold down, speedbar, rescan-project

>
> Thanks Mike, but I just don't see the rescan-project option.


Maybe you are in the wrong mode.
Try typing 'H' with the mouse in the speedbar.
Here's mine from suse 11
http://mysite.verizon.net/miketreseler/speedbar.png
>
> Here is what I do:
> open a .vhd file
> vhdl menu, select speedbar to open up the speedbar window
>
> When I right-click, hold down, speedbar: I don't see the rescan-
> project option. I see a list of options starting with Update, Auto-
> update, .... Customise, Close, Quit.


Hmm. That sounds like the VHDL, Options menu -- not the speedbar

> I don't quite understand your hint "center-click the project file".


That does a vhdl-set-file

> vhdl menu export project creates a .prj file. But this file doesn't
> show up in the speed bar? Is this the .prj file you are suggesting I
> center-click in the speedbar?


I don't use .prj files.
I use Vhdl, Project, Customize project.

Maybe you don't have a project defined?

Good luck.

-- Mike

http://mysite.verizon.net/miketreseler/speedbar.png
GNU Emacs 22.2.1 (i586-suse-linux-gnu, X toolkit, Xaw3d scroll bars)
of 2008-09-11 on yggdrasil
VHDL Mode 3.33.6 (2005-08-30)
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