FPGA Central

I'm working with a Spartan FPGA using ISE. I have a large array of 8
bit numbers, but due to the nature of the device, some of them are not
used. Is there a way to eliminate those particular registers so that
they don't take up space?

For example, if I have an array with 100 8-bit registers like this:

reg [7:0] array [99:0];

and I'm not using registers [22], [45], [66], or [92], can I somehow
remove those registers from the final design?

sid

"sid" <[email protected]> wrote in message
news:2059f53b-6bb3-4552-b918-a4fecaff421b@k30g2000hse.googlegroups.com...
> I'm working with a Spartan FPGA using ISE. I have a large array of 8
> bit numbers, but due to the nature of the device, some of them are not
> used. Is there a way to eliminate those particular registers so that
> they don't take up space?
>
> For example, if I have an array with 100 8-bit registers like this:
>
> reg [7:0] array [99:0];
>
> and I'm not using registers [22], [45], [66], or [92], can I somehow
> remove those registers from the final design?
>

Synthesis will automatically do that for you

KJ

KJ wrote:
> "sid" <[email protected]> wrote in message
> news:2059f53b-6bb3-4552-b918-a4fecaff421b@k30g2000hse.googlegroups.com...
>> I'm working with a Spartan FPGA using ISE. I have a large array of 8
>> bit numbers, but due to the nature of the device, some of them are
>> not used. Is there a way to eliminate those particular registers so
>> that they don't take up space?
>>
>> For example, if I have an array with 100 8-bit registers like this:
>>
>> reg [7:0] array [99:0];
>>
>> and I'm not using registers [22], [45], [66], or [92], can I somehow
>> remove those registers from the final design?
>>
>
> Synthesis will automatically do that for you
>
> KJ

KJ,
In some circumstances, maybe, but look at this scenario:-



process(clk,res)
begin
if res = '1' then
registers <= all_zeros;
elsif rising_edge(clk) then
registers(cpu_address) <= data_from_cpu;
end if;
end process;

data_to_cpu <= registers(cpu_address);



How does the synthesiser know which addresses the CPU never uses?

Cheers, Syms.

"Symon" <[email protected]> wrote in message
news:[email protected]...
> KJ wrote:
>> "sid" <[email protected]> wrote in message
>> news:2059f53b-6bb3-4552-b918-a4fecaff421b@k30g2000hse.googlegroups.com...
>>>
>>> and I'm not using registers [22], [45], [66], or [92], can I somehow
>>> remove those registers from the final design?
>>>
>>
>> Synthesis will automatically do that for you
>>
>> KJ
>
> KJ,
> In some circumstances, maybe, but look at this scenario:-
>
>
>
> process(clk,res)
> begin
> if res = '1' then
> registers <= all_zeros;
> elsif rising_edge(clk) then
> registers(cpu_address) <= data_from_cpu;
> end if;
> end process;
>
> data_to_cpu <= registers(cpu_address);
>
>
>
> How does the synthesiser know which addresses the CPU never uses?
>

It doesn't, and your example is not one where the registers are not used
either since they are all addressable therefore they must all be
implemented. If this is what the OP had in mind when he said he had
'unused' registers then he is mistaken as well.

KJ
> Cheers, Syms.
>
>
>
>
>

KJ wrote:
>
> It doesn't, and your example is not one where the registers are not
> used either since they are all addressable therefore they must all be
> implemented. If this is what the OP had in mind when he said he had
> 'unused' registers then he is mistaken as well.
>
> KJ


KJ,
You miss the point. How do I tell the synthesiser to ignore registers I'm
not going to use?
Cheers, Syms.

On Sun, 10 Aug 2008 13:42:55 +0100, "Symon" wrote:


>KJ,
>You miss the point.

Betcha he didn't *really* miss the point :-)

> How do I tell the synthesiser to ignore registers I'm
> not going to use?

even when you *do* use them, because all your writeable
registers are also readable? Well, I'd be tempted to
try to build a table of constants, indexed by register
address, specifying various interesting details of
each register. Better still, a table indexed by an
enum containing register *names*, so that each named
register's address can be specified separately.

A register's record in the table might contain, for example:
- a boolean to say whether it's implemented;
- is it writeable;
- which bits of it are populated.

Given such a table it's probably not too hard to write
a loop or maybe a generate-loop that creates the various
registers the way you want them (or, in sid's case,
don't want them).

I have always found the whole business of register-maps
a bit vexatious. Do you chuck all the registers into
one big 'orrible module, so that you can specify their
characteristics neatly in one place? That sounds nice,
until you realise that this module now has a bazillion
ports on it to carry the registers' contents to/from the
rest of the design. Or do you sprinkle the registers
around the design, so that you need only send the
common databus to each part of the design and the
physical I/O wiring is then localised to the place
where you need it? That sounds nice, until you note
that register addressing and configuration information
is then distributed across a slew of different design
files, and getting register readback organised nicely
is pretty tiresome too. Given that most FPGA-sized
designs only have one set of registers for the whole
thing, a centralised package for the config information
and distributed registers all of which access that
package's (constant) data seems like a reasonable
compromise. But I've never sorted out a solution
that I really like and is truly general.

cheers
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
[email protected]
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

"Symon" <[email protected]> wrote in message
news:[email protected]...
> KJ wrote:
>>
>> It doesn't, and your example is not one where the registers are not
>> used either since they are all addressable therefore they must all be
>> implemented. If this is what the OP had in mind when he said he had
>> 'unused' registers then he is mistaken as well.
>>
>> KJ
>
>
> KJ,
> You miss the point. How do I tell the synthesiser to ignore registers I'm
> not going to use?

You "tell the synthesizer", by not providing any mechanism for the output of
the register to have any impact on any external I/O pins. That's always the
way things get optimized away.

In your example you had the following statement:
data_to_cpu <= registers(cpu_address);

Therefore, even if the CPU *will* never write to a certain set of registers,
you've written code in such a way that synthesis must implement the entire
set of 'registers' since the output data_to_cpu depends on all of them. By
providing a meachanism for register(3) (as an example) to affect an output
signal, you've forced it to implement register(3). One relatively simple
way around this is the following:

data_to_cpu <= registers(Masker(cpu_address));

where 'Masker' is some function that maps the entire input address space
down to the allowable set of addresses. As a simple exercise, if 'Masker'
always returned 0 then the synthesis tool will get rid of registers 1 on up,
leaving only register(0). It will work as well for any other arbitrary
'Masker' function.

As a side note, if 'register(3)' was not needed, one might be tempted to
have a statement like register(3) <= (others <= '0') or some such. While
the synthesis tool will use such a statement and produce less logic it is
still implementing register(3), register(3) just happens to always return a
0. When all is said and done, doing it this way by having a set of 'zero
registers' may produce less logic;it would depend on just how complicated
the 'Masker' function gets.

KJ

I've found it easiest to create a constant is_used mask that mimics
the structure of the register array (so many words by so many bits,
etc.). Simply AND the written and read data bits with that mask, and
the synthesis tool will optimize away the register bits that are not
used (replacing them with constant zeroes). In the old days, I'd use a
for-generate/if-generate loop to infer the tri-state buffers for
reading each bit based on the mask. In creating the register and bit
assignments, I create integer constants for register address and
location of individual bits. For ranges of bits (bit fields), I create
a vector constant with the desired range, such that it can be accessed
as: register(address)(field'range). Then creating the masks is a self
documenting initialization statement:

constant is_used : reg_array_type :=
(register_name => (unused_bit_name, unused_field_name'range => '0',
others => '1'),...);

Alternatively, you can list the used bits and default the others to 0,
depending on which list is shorter.

I also use a writable mask (register level, not bit level, since we
generally decree that all cpu-writable registers return their written
data when read) to handle read-only vs read=write registers in the
same array.

Andy