FPGA Central

Hi there,

I have attached a posting from linuxppc-embedded which offers a little
clarification and asks for those with similar experiences to respond.

Cheers,

Jon.

Hi there,

Added configuration options to Linux config.in to control (actual names
are slightly different for internal naming convention):

CACHE_MODE - Toggle these
CACHE_REAL - Real mode cacheing enabled
CACHE_KERNEL - Kernel pages cacheing enabled
CACHE_USER - User pages cacheing enabled

The system now boots if I disable all cacheing and it seems to be ok.
However this only partially helps me and I still welcome input.

Anyone know of any particular reason why this Memec Insight board would
dislike cacheing being enabled especially with EDK6.1 hardware?

I would love to hand validate the cache contents and this kind of thing
but the Xilinx documentation is not good. The Xilinx XMD FAQ says that
icachestartadr is a command when in fact it is a parameter to ppcconnect
and then fails to provide an actual example of its use. *Sigh*.

Cheers,

Jon.