FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 11-12-2007, 12:16 PM
Pasacco
Guest
 
Posts: n/a
Default [EDK tool] simulation setup

Dear

I need to simulate my EDK (8.2) project.

Simulator is Modelsim SE 6.1c.

I did following steps:

-------------------------------------------
In order to compile COMPXLIB,

I used the EDK simulation library compilation wizard

Project -> Project options -> HDL and Simulation -> Simulation library
path

EDK library = C:/EDK/EDK_LIB
Xilinx library = C:/Xilinx/Xilinx_LIB
-------------------------------------------

However, I could not proceed, because of the message "Modelsim is not
found. Please ensure that the simulator is correctly installed and/or
necessary environment settings are available".

Could anyone tell me "how to set up the environment" (or, how to
points to the location of the simulator)? in EDK 8.2 ?

Thank you in advance

Reply With Quote
  #2 (permalink)  
Old 11-12-2007, 07:25 PM
Mike Treseler
Guest
 
Posts: n/a
Default Re: [EDK tool] simulation setup

Pasacco wrote:

> Could anyone tell me "how to set up the environment" (or, how to
> points to the location of the simulator)? in EDK 8.2 ?


Click up a shell, bash or cmd.exe

mkdir play
cd play
vcom

If this doesn't give you the vcom usage,
type "exit" to close the shell,
find vcom, and add it's location
to your path and try again.

-- Mike Treseler
Reply With Quote
Reply

Bookmarks


Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Simulation tool leaf FPGA 3 03-21-2006 05:40 PM
$50 Verilog Simulation tool [email protected] Verilog 0 07-31-2005 08:08 AM
Problem in Xilinx Rocket IO Simulation using HyperLynx SI tool Ravi FPGA 1 10-13-2004 05:40 PM
XST Tool - Want a verilog simulation netlist Varun Jindal FPGA 2 09-30-2004 12:16 PM
Simulation Tool with Video Display Brad Smallridge FPGA 1 06-28-2004 03:38 AM


All times are GMT +1. The time now is 12:03 PM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2024, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved