Hi,
I am currenty trying to write a definition file for the board we are
developing. Our
FPGA (XC2V6000) is connected to a ISSI SRAM with a data
width of 8 bit. The OPB External Memory Controller datasheed says I have
controll over the parameter C_MEMX_WIDTH which describes the width of
the x-th memorybank data bus. Unfortunately the EDK ports (in the .mhs
file) my interface on a 32 bit data bus, like this:
PORT Mem_DQ = 0b000000000000000000000000 & fpga_0_SRAM_256Kx8_Mem_DQ
Synthesising this fails.
Any idea how to tell EDK that it shall generate a 8-bit SRAM-Interface?
Thank you anyway,
C. Lauer