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  #1 (permalink)  
Old 11-13-2007, 07:58 PM
Pasacco
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Posts: n/a
Default [EDK simulation] synopsys translate_off

Dear

I would like to ask some help, for simulating EDK project.

I did following steps:

--------------------------------------------------------------------------------
1. Generate "simulation model and compiler script" using EDK 8.2 tool.

2. Compile design.
" do system.do"

Following error ocurred:

-----------------------
# ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/
clock_dcm.vhd(19): Library virtex2 not found.
# ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/
clock_dcm.vhd(20): (vcom-1136) Unknown identifier "virtex2".
-----------------------

In the "clock_dcm.vhd", I commented following library definition:
-----------------------
-- synopsys translate_off
-- library virtex2;
-- use virtex2.all;
-- synopsys translate_on
-----------------------

Now "system.do" is compiled.

3. Load design

"vsim system"

Following warning occurred:

-----------------------
Warning: Component instance "ramx32 : ramb16_s36_s36" is not bound.
-----------------------

This means that BRAM block is present.
I ignored this warning and proceeded to next step:

4. Run simulation

Finally, following error occurred:

-----------------------
# ** Fatal: (vsim-3421) Value 127 is out of range 0 to 5.
# Time: 0 ns Iteration: 12 Process: /testbench/uut/buffer/out_mux
File: C:/Work/TEST/SimpleEDK8.2/pcores/Buffer_Wrapper_v1_00_a/hdl/vhdl/
buffer.vhd
# Fatal error in Process out_mux at
-----------------------

This looks like a logical error in VHDL.
But this VHDL file is provided by the board vendor.
I think I made mistake in the simulation process.

--------------------------------------------------------------------------------

My question is that

If I need to use following library "virtex2", how can I generate this
library "virtex2"?

-----------------------
-- synopsys translate_off
library virtex2;
use virtex2.all;
-- synopsys translate_on
-----------------------

Thank you again.

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  #2 (permalink)  
Old 11-15-2007, 02:33 AM
Guest
 
Posts: n/a
Default Re: synopsys translate_off

This error is because you dont have Xilinx UNISIM and XILINXCORELIB
libraries mapped in Modelsim.

-- Generate the libraries in EDK
-- Add your libraries to your Modelsim.ini file

-- Then when you are using "vcom" (equivalent of "Start Simulation"
button in Modelsim) , add "-L XILINXCORELIB_VER -L UNISIM" to your
command line flow. This will link your Xilinx components against these
libraries.

Then you should be able to simulate..

Hope this helps..

-- parag


On Nov 13, 12:58 pm, Pasacco <[email protected]> wrote:
> Dear
>
> I would like to ask some help, for simulating EDK project.
>
> I did following steps:
>
> --------------------------------------------------------------------------------
> 1. Generate "simulation model and compiler script" using EDK 8.2 tool.
>
> 2. Compile design.
> " do system.do"
>
> Following error ocurred:
>
> -----------------------
> # ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/
> clock_dcm.vhd(19): Library virtex2 not found.
> # ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/
> clock_dcm.vhd(20): (vcom-1136) Unknown identifier "virtex2".
> -----------------------
>
> In the "clock_dcm.vhd", I commented following library definition:
> -----------------------
> -- synopsys translate_off
> -- library virtex2;
> -- use virtex2.all;
> -- synopsys translate_on
> -----------------------
>
> Now "system.do" is compiled.
>
> 3. Load design
>
> "vsim system"
>
> Following warning occurred:
>
> -----------------------
> Warning: Component instance "ramx32 : ramb16_s36_s36" is not bound.
> -----------------------
>
> This means that BRAM block is present.
> I ignored this warning and proceeded to next step:
>
> 4. Run simulation
>
> Finally, following error occurred:
>
> -----------------------
> # ** Fatal: (vsim-3421) Value 127 is out of range 0 to 5.
> # Time: 0 ns Iteration: 12 Process: /testbench/uut/buffer/out_mux
> File: C:/Work/TEST/SimpleEDK8.2/pcores/Buffer_Wrapper_v1_00_a/hdl/vhdl/
> buffer.vhd
> # Fatal error in Process out_mux at
> -----------------------
>
> This looks like a logical error in VHDL.
> But this VHDL file is provided by the board vendor.
> I think I made mistake in the simulation process.
>
> --------------------------------------------------------------------------------
>
> My question is that
>
> If I need to use following library "virtex2", how can I generate this
> library "virtex2"?
>
> -----------------------
> -- synopsys translate_off
> library virtex2;
> use virtex2.all;
> -- synopsys translate_on
> -----------------------
>
> Thank you again.


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  #3 (permalink)  
Old 11-15-2007, 07:27 PM
Pasacco
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Posts: n/a
Default Re: synopsys translate_off

Dear
I could not resove this problem.

UNISIM and XILINXCORELIB are properly mapped to Modelsim.

The thing is that

The VHDL files "in Pcore directory" contain following:
(BRAMs are instantiated in the VHDL.)

--------------------------------------
-- pragma translate_off
library VIRTEX2;
use VIRTEX2.all;
-- pragma translate_on
--------------------------------------

When I try "do system.do", error occurred "Virtex2 library not found".

When I comment the "Virtex2 library declaration" and I try "do
system.do",
no error and no warning occurred.

--------------------------------------
-- pragma translate_off
--library VIRTEX2;
--use VIRTEX2.all;
-- pragma translate_on
--------------------------------------

Problem is that

When I try "vcom -work work testbench.vhd", then following warning
occurs.

-----------------------
Warning: Component instance "ramx32 : ramb16_s36_s36" is not bound.
-----------------------

This means that BRAM block is disappeared.

As a result, I do not see any signal toggling in the waveform in
Modelsim.

My question is that

What does the following mean?
How can we find the library "VIRTEX2" and map?
--------------------------------------
-- pragma translate_off
library VIRTEX2;
use VIRTEX2.all;
-- pragma translate_on
--------------------------------------

Thank you for reply in advance.
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  #4 (permalink)  
Old 11-15-2007, 07:57 PM
Colin Paul Gloster
Guest
 
Posts: n/a
Default Re: synopsys translate_off

In
news:[email protected]m
timestamped Thu, 15 Nov 2007 10:27:24 -0800 (PST), Pasacco
<[email protected]> posted:
|----------------------------------------------------------------------|
|"[..] |
| |
|My question is that |
| |
|What does the following mean? |
|How can we find the library "VIRTEX2" and map? |
|-------------------------------------- |
|-- pragma translate_off |
|library VIRTEX2; |
|use VIRTEX2.all; |
|-- pragma translate_on |
|-------------------------------------- |
| |
|Thank you for reply in advance." |
|----------------------------------------------------------------------|

-- pragma translate_off is to inform Synopsys to not to try to
synthesize the following code before -- pragma translate_on. The
intention is to allow code which can be e.g. simulated but which is
not to be synthesized, but you are experiencing a problem in getting
the simulation to run. Is it extremely important to you to have a
precise model of the BRAM? Would it be acceptable to substitute the
synthesized Virtex2's BRAMs with a functional generic RAM in the simulation?
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  #5 (permalink)  
Old 11-15-2007, 08:26 PM
Pasacco
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Posts: n/a
Default Re: synopsys translate_off

> -- pragma translate_off is to inform Synopsys to not to try to
> synthesize the following code before -- pragma translate_on. The
> intention is to allow code which can be e.g. simulated but which is
> not to be synthesized, but you are experiencing a problem in getting
> the simulation to run. Is it extremely important to you to have a
> precise model of the BRAM? Would it be acceptable to substitute the
> synthesized Virtex2's BRAMs with a functional generic RAM in the simulation?


When I simulate, I do not see any signal toggling in the waveform,
because BRAMs are unconnected.

Actually the "pcores" are provided by a vendor.
I could modify the VHDL code, but it is too time consuming.
According to your reply, there might exist "specific Virtex2" library
for the BRAMs.
Are there any way to find the Virtex2 library, to simulate with
Modelsim?
Thank you for reply.
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  #6 (permalink)  
Old 11-15-2007, 09:05 PM
Pasacco
Guest
 
Posts: n/a
Default Re: synopsys translate_off

Thank you for reply.

When I simulate, I do not see any signal toggling in the waveform,
because BRAMs are unconnected.

Actually the "pcores" are provided by a vendor.
I could modify the VHDL code, but it is too time consuming.
According to your reply, there might exist "specific Virtex2" library
for the BRAMs.

Name of the BRAM primitive is "ram_dp".

Are there any way to find the Virtex2 library, to simulate with
Modelsim?

Maybe my problem is not a "library problem".
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  #7 (permalink)  
Old 11-15-2007, 09:30 PM
Duane Clark
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Posts: n/a
Default Re: synopsys translate_off

Pasacco wrote:
> Thank you for reply.
>
> When I simulate, I do not see any signal toggling in the waveform,
> because BRAMs are unconnected.
>
> Actually the "pcores" are provided by a vendor.
> I could modify the VHDL code, but it is too time consuming.
> According to your reply, there might exist "specific Virtex2" library
> for the BRAMs.
>
> Name of the BRAM primitive is "ram_dp".


I am a little puzzled by that statement. Earlier you said:

> When I try "vcom -work work testbench.vhd", then following warning
> occurs.
>
> -----------------------
> Warning: Component instance "ramx32 : ramb16_s36_s36" is not bound.
> -----------------------


In that case, the BRAM primitive name is ramb16_s36_s36. That primitive
is a standard one available in the Xilinx unisim library.

>
> Are there any way to find the Virtex2 library, to simulate with
> Modelsim?
>
> Maybe my problem is not a "library problem".


Yes, it is a library problem. Your vendor appears to be doing things in
a weird way, and a bit more info is needed to figure out what they are
doing.

Show all the library declarations in the file (not just the virtex2 ones).

If there is a component declaration for the bram at the beginning of the
architecture (that is, before the 'begin' statement), show that.

Show the component instantiation of the bram within the body of the
architecture. If there are multiple instantiations, just show one.
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  #8 (permalink)  
Old 11-16-2007, 03:35 AM
Guest
 
Posts: n/a
Default Re: synopsys translate_off

You still are not adding the Library stuff when you are calling "vcom"

vcom -L XILINXCORELIB_VER -L UNISIM work.testbench

Hope this helps.

-- parag

On Nov 15, 12:27 pm, Pasacco <[email protected]> wrote:
> Dear
> I could not resove this problem.
>
> UNISIM and XILINXCORELIB are properly mapped to Modelsim.
>
> The thing is that
>
> The VHDL files "in Pcore directory" contain following:
> (BRAMs are instantiated in the VHDL.)
>
> --------------------------------------
> -- pragma translate_off
> library VIRTEX2;
> use VIRTEX2.all;
> -- pragma translate_on
> --------------------------------------
>
> When I try "do system.do", error occurred "Virtex2 library not found".
>
> When I comment the "Virtex2 library declaration" and I try "do
> system.do",
> no error and no warning occurred.
>
> --------------------------------------
> -- pragma translate_off
> --library VIRTEX2;
> --use VIRTEX2.all;
> -- pragma translate_on
> --------------------------------------
>
> Problem is that
>
> When I try "vcom -work work testbench.vhd", then following warning
> occurs.
>
> -----------------------
> Warning: Component instance "ramx32 : ramb16_s36_s36" is not bound.
> -----------------------
>
> This means that BRAM block is disappeared.
>
> As a result, I do not see any signal toggling in the waveform in
> Modelsim.
>
> My question is that
>
> What does the following mean?
> How can we find the library "VIRTEX2" and map?
> --------------------------------------
> -- pragma translate_off
> library VIRTEX2;
> use VIRTEX2.all;
> -- pragma translate_on
> --------------------------------------
>
> Thank you for reply in advance.






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  #9 (permalink)  
Old 11-16-2007, 11:51 AM
Pasacco
Guest
 
Posts: n/a
Default Re: synopsys translate_off

It turned out that virtex2 library was not necessary for the "post
PAR" simulation.
It was a mess with different warnings, different logical errors,
library settings.
After I fixed a logical error in my "pcore" and I mapped the "unisim,
xilinxcorelib, xilinxcorelib_ver" in "modelsim.ini",
I see signal toggling that I expected.
Many thanks to Duane Clark, Colin Paul Gloster, beeraka.
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