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Old 11-29-2007, 03:38 PM
Anton Kowalski
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Default EDK IPIF development workflow

I am new to EDK (but not ISE) and have some questions about the
workflow for developing a custom IPIF peripheral.

The documentation implies that the peripheral is re-imported into EDK
once it's development is *complete*. But what if one wants to work
iteratively? That is, I would like to start with a stubbed-out design
(the one provided in user_logic.vhd) and add to it incrementally,
debugging and testing the peripheral from the processor along the way.
Is there a simple way to do this? Or does one have to re-import the
design every time a internal structural change is made? (The external
specification will remain the same.)

Thanks,
Anton
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Old 11-29-2007, 04:28 PM
John McCaskill
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Default Re: EDK IPIF development workflow

On Nov 29, 9:38 am, Anton Kowalski <[email protected]> wrote:
> I am new to EDK (but not ISE) and have some questions about the
> workflow for developing a custom IPIF peripheral.
>
> The documentation implies that the peripheral is re-imported into EDK
> once it's development is *complete*. But what if one wants to work
> iteratively? That is, I would like to start with a stubbed-out design
> (the one provided in user_logic.vhd) and add to it incrementally,
> debugging and testing the peripheral from the processor along the way.
> Is there a simple way to do this? Or does one have to re-import the
> design every time a internal structural change is made? (The external
> specification will remain the same.)
>
> Thanks,
> Anton


In the MPD file for your peripheral, add the line:

OPTION CORE_STATE = DEVELOPMENT

This will cause EDK to not cache the synthesis results for your
peripheral. For simulation, I just use the clean option, then
regenerate the simulation files if I change the peripheral. If you
are not changing the data files (MPD, TCL, etc), you do not need to
rescan the repository.

If you are creating your own peripheral in EDK, you will want to read
the "Platform Specification Format Reference Manual" located at $EDK/
doc/psf_rm.pdf

Regards,

John McCaskill
www.fastertechnology.com


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  #3 (permalink)  
Old 12-05-2007, 09:34 AM
comp.arch.fpga
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Default Re: EDK IPIF development workflow

On 29 Nov., 16:38, Anton Kowalski <[email protected]> wrote:
> I am new to EDK (but not ISE) and have some questions about the
> workflow for developing a custom IPIF peripheral.
>
> The documentation implies that the peripheral is re-imported into EDK
> once it's development is *complete*. But what if one wants to work
> iteratively? That is, I would like to start with a stubbed-out design
> (the one provided in user_logic.vhd) and add to it incrementally,
> debugging and testing the peripheral from the processor along the way.
> Is there a simple way to do this? Or does one have to re-import the
> design every time a internal structural change is made? (The external
> specification will remain the same.)


Let me tell you some lessons that I learned over my last couple of EDK
projects.

1.
The address decodes and register implementation in user_logic. vhd ist
awfull.
I stripped out 2ns from the critical path with 5 minutes of editing.

2.
In the design flow we are using we have a rather stable CPU system
with complex
hardware in development. When implementing the user logic in the EDK
project
every time you add a register you need to open EDK, change and wire up
multiple
hierarchy levels of entities and component declaration, etc.

The solution to both problems is simple:
We create an IPIF with only one user address range. Usually with a
size of 24 bits.
(Larger address range means less hardware in the decoders)

Instead of instantiating the user logic inside EDK we bring out the
IPIF signals to
ports of the EDK system. We instantiate the EDK system in an ISE
project and
implement the user logic there, doing our own address decoding.
This greatly speeds up iterations on the register set. We hardly ever
touch EDK
again during the design process.

Kolja Sulimma





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