FPGA Central

Hi,

I have created a periperal IP device using the "Create/Import.." wizard of the EDK 6.3. The IP has 4 32 bit registers. I have been able to connect the IP as a slave to the OPB and write a small program that can write and read these registers. However when I make changes in the vhdl files of the IP it seems to have no effect. I tried reading one of the four registers return a constant value but it still returns the value I previously read .. Do I have do soemthing to make the EDK update the IP?

thanks

Peter Soerensen wrote:
> Hi,
>
> I have created a periperal IP device using the "Create/Import.."
> wizard of the EDK 6.3. The IP has 4 32 bit registers. I have been
> able to connect the IP as a slave to the OPB and write a small
> program that can write and read these registers. However when I make
> changes in the vhdl files of the IP it seems to have no effect. I
> tried reading one of the four registers return a constant value but
> it still returns the value I previously read .. Do I have do
> soemthing to make the EDK update the IP?
>

First, let me say that I am not using the EDK GUI except to create an
initial project. Thereafter, I make all changes with a normal text
editor, and compile by executing make commands at the command line (on
Linux). So keep that in mind when reading my comments.

I also noticed that when I made changes to one of the cores in my
project's pcores directory, that the changes were not automatically
compiled in. Eventually, I discovered somewhere in the EDK documentation
that you had to set a flag somewhere for that to happen (I don't
remember the flag, or where it was in the docs). Unfortunately, once I
set the flag, EDK insisted on recompiling the core every time, rather
than when a change had been made to the code.

So instead I hand edited the makefiles. In system_incl.make, I added
lines that look like:

MY_DDR_CLOCKS_IMPLN = implementation/my_ddr_clocks_wrapper.ngc
MY_DDR_CLOCKS_FILES = pcores/ddr_clocks_v1_00_a/hdl/vhdl/ddr_clocks.vhd \
pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.mpd \
pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.pao

MY_DIMM_IMPLN = implementation/my_dimm_wrapper.ngc
MY_DIMM_FILES = pcores/wsoa_dimm_v1_00_a/hdl/vhdl/clock_gen.vhd \
pcores/wsoa_dimm_v1_00_a/hdl/vhdl/command_statemachine.vhd \
pcores/wsoa_dimm_v1_00_a/hdl/vhdl/coregen_comp_defs.vhd \
....

MY_BITS_IMPLN = implementation/my_bits_wrapper.ngc
MY_BITS_FILES = pcores/plb_bits_v1_00_a/hdl/vhdl/bits_core.vhd \
pcores/plb_bits_v1_00_a/hdl/vhdl/plb_ipif_ssp1.vhd \
pcores/plb_bits_v1_00_a/hdl/vhdl/plb_bits.vhd \
....

MY_WRAPPER_NGC_FILES = $(MY_DDR_CLOCKS_IMPLN) \
$(MY_DIMM_IMPLN) $(MY_BITS_IMPLN)

MY_DEVELOPMENT_FILES = $(MY_DDR_CLOCKS_FILES) \
$(MY_DIMM_FILES) $(MY_BITS_FILES)

Then in system.make, I have lines that look like:

################################################## ###############
# HARDWARE IMPLEMENTATION FLOW
################################################## ###############

$(MY_DDR_CLOCKS_IMPLN): $(MY_DDR_CLOCKS_FILES)
rm -f implementation/my_ddr_clocks_wrapper.ngc
rm -f implementation/cache/my_ddr_clocks_wrapper.ngc

$(MY_DIMM_IMPLN): $(MY_DIMM_FILES)
rm -f implementation/my_dimm_wrapper.ngc
rm -f implementation/cache/my_dimm_wrapper.ngc

$(MY_BITS_IMPLN): $(MY_BITS_FILES)
rm -f implementation/my_bits_wrapper.ngc
rm -f implementation/cache/my_bits_wrapper.ngc

implementation/$(SYSTEM).bmm \
$(CORE_WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
$(MY_DEVELOPMENT_FILES)
@echo "************************************************* ***"
@echo "Creating system netlist for hardware specification.."
@echo "************************************************* ***"
platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE)

A little extra effort, but well worth it in the end for me.

--
My real email is akamail.com@dclark (or something like that).

Hi Peter,

I think that the easy way for you to update your peripheral
functionally is to re-import your peripheral(using the wizard) after
updating your vhdl files (user_logic.vhd and the peripheral_name??.vhd)
that way (i believe..) it will work just fine.

Regards, Moti.

indeed, i did it like that afterwards and i have both (with and without the
wizard) working heheh ...

thanx for the advice ...
"Moti" <[email protected]> wrote in message
news:[email protected] oups.com...
> Hi Peter,
>
> I think that the easy way for you to update your peripheral
> functionally is to re-import your peripheral(using the wizard) after
> updating your vhdl files (user_logic.vhd and the peripheral_name??.vhd)
> that way (i believe..) it will work just fine.
>
> Regards, Moti.
>

idd, that was one of the reasons ... i also started to do everything in a
different editor and just compile in EDK ... thanx for the information ...


"Duane Clark" <[email protected]> wrote in message
news:[email protected]...
> Peter Soerensen wrote:
> > Hi,
> >
> > I have created a periperal IP device using the "Create/Import.."
> > wizard of the EDK 6.3. The IP has 4 32 bit registers. I have been
> > able to connect the IP as a slave to the OPB and write a small
> > program that can write and read these registers. However when I make
> > changes in the vhdl files of the IP it seems to have no effect. I
> > tried reading one of the four registers return a constant value but
> > it still returns the value I previously read .. Do I have do
> > soemthing to make the EDK update the IP?
> >
>
> First, let me say that I am not using the EDK GUI except to create an
> initial project. Thereafter, I make all changes with a normal text
> editor, and compile by executing make commands at the command line (on
> Linux). So keep that in mind when reading my comments.
>
> I also noticed that when I made changes to one of the cores in my
> project's pcores directory, that the changes were not automatically
> compiled in. Eventually, I discovered somewhere in the EDK documentation
> that you had to set a flag somewhere for that to happen (I don't
> remember the flag, or where it was in the docs). Unfortunately, once I
> set the flag, EDK insisted on recompiling the core every time, rather
> than when a change had been made to the code.
>
> So instead I hand edited the makefiles. In system_incl.make, I added
> lines that look like:
>
> MY_DDR_CLOCKS_IMPLN = implementation/my_ddr_clocks_wrapper.ngc
> MY_DDR_CLOCKS_FILES = pcores/ddr_clocks_v1_00_a/hdl/vhdl/ddr_clocks.vhd \
> pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.mpd \
> pcores/ddr_clocks_v1_00_a/data/ddr_clocks_v2_1_0.pao
>
> MY_DIMM_IMPLN = implementation/my_dimm_wrapper.ngc
> MY_DIMM_FILES = pcores/wsoa_dimm_v1_00_a/hdl/vhdl/clock_gen.vhd \
> pcores/wsoa_dimm_v1_00_a/hdl/vhdl/command_statemachine.vhd \
> pcores/wsoa_dimm_v1_00_a/hdl/vhdl/coregen_comp_defs.vhd \
> ...
>
> MY_BITS_IMPLN = implementation/my_bits_wrapper.ngc
> MY_BITS_FILES = pcores/plb_bits_v1_00_a/hdl/vhdl/bits_core.vhd \
> pcores/plb_bits_v1_00_a/hdl/vhdl/plb_ipif_ssp1.vhd \
> pcores/plb_bits_v1_00_a/hdl/vhdl/plb_bits.vhd \
> ...
>
> MY_WRAPPER_NGC_FILES = $(MY_DDR_CLOCKS_IMPLN) \
> $(MY_DIMM_IMPLN) $(MY_BITS_IMPLN)
>
> MY_DEVELOPMENT_FILES = $(MY_DDR_CLOCKS_FILES) \
> $(MY_DIMM_FILES) $(MY_BITS_FILES)
>
> Then in system.make, I have lines that look like:
>
> ################################################## ###############
> # HARDWARE IMPLEMENTATION FLOW
> ################################################## ###############
>
> $(MY_DDR_CLOCKS_IMPLN): $(MY_DDR_CLOCKS_FILES)
> rm -f implementation/my_ddr_clocks_wrapper.ngc
> rm -f implementation/cache/my_ddr_clocks_wrapper.ngc
>
> $(MY_DIMM_IMPLN): $(MY_DIMM_FILES)
> rm -f implementation/my_dimm_wrapper.ngc
> rm -f implementation/cache/my_dimm_wrapper.ngc
>
> $(MY_BITS_IMPLN): $(MY_BITS_FILES)
> rm -f implementation/my_bits_wrapper.ngc
> rm -f implementation/cache/my_bits_wrapper.ngc
>
> implementation/$(SYSTEM).bmm \
> $(CORE_WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
> $(MY_DEVELOPMENT_FILES)
> @echo "************************************************* ***"
> @echo "Creating system netlist for hardware specification.."
> @echo "************************************************* ***"
> platgen $(PLATGEN_OPTIONS) -st xst $(MHSFILE)
>
> A little extra effort, but well worth it in the end for me.
>
> --
> My real email is akamail.com@dclark (or something like that).