FPGA Central

Hello,

In our *working* EDK 8.1i project, we locked a DCM in the following
manner in the UCF file (located in <proj_dir>/data/system.ucf):


INST dcm_sys/dcm_sys/DCM_INST LOC = DCM_X0Y0;
INST ppc405_0/ppc405_0/PPC405_i LOC = PPC405_X1Y0;

The dcm module, named "dcm_sys" in the MHS file did not give us any
problems in 8.1i. However, taking the same project (i.e. same MHS, UCF
files) and syncing-up to EDK 9.1, I now get the following error during
a bit stream generation (in the file xflow.log):


ERROR:NgdBuild:752 - "system.ucf" Line 19: Could not find instance(s)
'dcm_sys/dcm_sys/DCM_INST' in the design. To suppress this error,
specify
the correct instance name or remove the constraint. The 'Allow
Unmatched LOC
Constraints' ISE property can also be set ( -aul switch for
command line

It seems like that the way that EDK looks at the organization of
top-level modules in the MHS file is now different. Any pointers? I
tried changing "dcm_sys/dcm_sys/DCM_INST" to "dcm_sys/DCM_INST", but
that failed. I suppose I can remove the constrait, but someone else
placed that constraint for a reason....

Thanks,

NN

Nju Njoroge wrote:
> Hello,
>
> In our *working* EDK 8.1i project, we locked a DCM in the following
> manner in the UCF file (located in <proj_dir>/data/system.ucf):
[snip]...

comment out the DCM LOC in your .ucf file, then run place and route.
Open the design in FPGA Editor, find the DCM and look at the instance
name. Now uncomment the DCM LOC and substitute the instance name that
ISE 9.1i assigned. Rerun the place and route.

---
Joe Samson
Pixel Velocity

On May 20, 10:26 am, Joseph Samson <[email protected]>
wrote:
> Nju Njorogewrote:
> > Hello,
>
> > In our *working* EDK 8.1i project, we locked aDCMin the following
> > manner in the UCF file (located in <proj_dir>/data/system.ucf):
>
> [snip]...
>
> comment out theDCMLOC in your .ucf file, then run place and route.
> Open the design in FPGA Editor, find theDCMand look at the instance
> name. Now uncomment theDCMLOC and substitute the instance name that
> ISE 9.1i assigned. Rerun the place and route.
Great suggestion. I tried it and this is the name it uses: dcm_sys/
dcm_sys/Using_Virtex.DCM_INST

For some reason, the new tools appended a prefix "Using_Virtex" to the
DCM_INST.

Answer record 23249 outlines this change:
http://www.xilinx.com/xlnx/xil_ans_d...PagePath=23249


Nju Njoroge wrote:
> On May 20, 10:26 am, Joseph Samson <[email protected]>
> wrote:
>> Nju Njorogewrote:
>>> Hello,
>>> In our *working* EDK 8.1i project, we locked aDCMin the following
>>> manner in the UCF file (located in <proj_dir>/data/system.ucf):
>> [snip]...
>>
>> comment out theDCMLOC in your .ucf file, then run place and route.
>> Open the design in FPGA Editor, find theDCMand look at the instance
>> name. Now uncomment theDCMLOC and substitute the instance name that
>> ISE 9.1i assigned. Rerun the place and route.
> Great suggestion. I tried it and this is the name it uses: dcm_sys/
> dcm_sys/Using_Virtex.DCM_INST
>
> For some reason, the new tools appended a prefix "Using_Virtex" to the
> DCM_INST.
>