FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 01-10-2005, 06:31 PM
Grégory Mermoud
Guest
 
Posts: n/a
Default Editing bitstream

Hi all!

I am currently looking for an application note, a tech report or
anything else that deals with Xilinx Spartan2 bitstream structure in
order to edit bitstreams for this FPGA.

Someone has ever tried to do that ?

Cheers,

Grégory
Reply With Quote
  #2 (permalink)  
Old 01-10-2005, 06:58 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Editing bitstream

Gregory, you have to be more specific about what you want to edit:
BlockRAM content: easy
LUTs: not too difficult
Interconnect structure: forget it

Peter Alfke

Reply With Quote
  #3 (permalink)  
Old 01-10-2005, 07:53 PM
Nicholas Weaver
Guest
 
Posts: n/a
Default Re: Editing bitstream

In article <[email protected] .com>,
Peter Alfke <[email protected]> wrote:
>Gregory, you have to be more specific about what you want to edit:
>BlockRAM content: easy
>LUTs: not too difficult
>Interconnect structure: forget it


If you REALLY want to edit interconnect structure on a Xilinx FPGA,
use one supported by JBits. But you really, REALLY don't want to.
--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu
Reply With Quote
  #4 (permalink)  
Old 01-10-2005, 09:39 PM
Falk Brunner
Guest
 
Posts: n/a
Default Re: Editing bitstream


"Nicholas Weaver" <[email protected]> schrieb im Newsbeitrag
news:[email protected]

> If you REALLY want to edit interconnect structure on a Xilinx FPGA,
> use one supported by JBits. But you really, REALLY don't want to.


Is there a practical reason to do so??
Cant think of such a reason.

Regards
Falk





Reply With Quote
  #5 (permalink)  
Old 01-10-2005, 11:07 PM
Grégory Mermoud
Guest
 
Posts: n/a
Default Re: Editing bitstream

Peter Alfke wrote:
> Gregory, you have to be more specific about what you want to edit:
> BlockRAM content: easy
> LUTs: not too difficult
> Interconnect structure: forget it
>
> Peter Alfke
>


LUTs. But thanks, xapp151 came and told me the truth about it

But it does not seem to be "not too difficult" as you say. I need to
make it completely automatic through a C program.

Maybe do you know any tutorial or further paper or application note
concerning this problem ?
Reply With Quote
  #6 (permalink)  
Old 01-11-2005, 12:45 AM
Nicholas Weaver
Guest
 
Posts: n/a
Default Re: Editing bitstream

In article <[email protected]>,
Falk Brunner <[email protected]> wrote:
>> If you REALLY want to edit interconnect structure on a Xilinx FPGA,
>> use one supported by JBits. But you really, REALLY don't want to.

>
>Is there a practical reason to do so??
>Cant think of such a reason.


A researcher working on routing algorithms.

A researcher looking to reroute designs to better handle partial
configuration.

A researcher looking at how to deal with a large board of flawed FPGAs
(a'la the old HP system), especially with easypath parts testing the
LUT fully but not fully testing the interconnect.

>Regards
>Falk
>
>
>
>
>



--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu
Reply With Quote
  #7 (permalink)  
Old 01-11-2005, 07:02 PM
Falk Brunner
Guest
 
Posts: n/a
Default Re: Editing bitstream

"Nicholas Weaver" <[email protected]> schrieb im Newsbeitrag
news:[email protected]

> >Is there a practical reason to do so??
> >Cant think of such a reason.

>
> A researcher working on routing algorithms.
>
> A researcher looking to reroute designs to better handle partial
> configuration.
>
> A researcher looking at how to deal with a large board of flawed FPGAs
> (a'la the old HP system), especially with easypath parts testing the
> LUT fully but not fully testing the interconnect.


But this all is stuff done only by the Xilinx folks or people working close
to Xilinx to improve the design flow tools (map/ p&R). And those guy for
sure have much more detailed information (and tools) about FPGA
connectivity. No normal mortal, ahhh user, does this kind of stuff, not
even advanced users.
But I wont stop anyone.

Regards
Falk



Reply With Quote
  #8 (permalink)  
Old 01-11-2005, 07:43 PM
Nicholas Weaver
Guest
 
Posts: n/a
Default Re: Editing bitstream

In article <[email protected]>,
Falk Brunner <[email protected]> wrote:

>But this all is stuff done only by the Xilinx folks or people working close
>to Xilinx to improve the design flow tools (map/ p&R). And those guy for
>sure have much more detailed information (and tools) about FPGA
>connectivity. No normal mortal, ahhh user, does this kind of stuff, not
>even advanced users.
>But I wont stop anyone.


Uh, you'd be suprised what a researcher would want to do. EG, one
research bit I did loaded Xilinx designs after placement but before
routing, ripped up all the registers, duplicated them for C-slowing,
retimed, reinserted all the new registers, and wrote back out the
placement.

I could EASILY see an interesting research project which "meer mortal
researchers" could attempt which would be take a bunch of easypath
parts, map the actual defects, and route around defets albeit at a
performance penalty.

It might be interesting to see if you colud use this to build a
multi-teraflop vector supercomputer on a decent budget.
--
Nicholas C. Weaver. to reply email to "nweaver" at the domain
icsi.berkeley.edu
Reply With Quote
  #9 (permalink)  
Old 01-11-2005, 10:10 PM
Peter Alfke
Guest
 
Posts: n/a
Default Re: Editing bitstream


Nicholas Weaver wrote:
>> I could EASILY see an interesting research project which "meer

mortal
> researchers" could attempt which would be take a bunch of easypath
> parts, map the actual defects, and route around defets albeit at a
> performance penalty.


Nick,
as you know, there is no "bunch of EasyPath parts". By the nature of
the beast, each and every one part is different. That makes your
suggestion a formidably inefficient job...

Peter Alfke

Reply With Quote
  #10 (permalink)  
Old 01-12-2005, 07:13 PM
Falk Brunner
Guest
 
Posts: n/a
Default Re: Editing bitstream


"Nicholas Weaver" <[email protected]> schrieb im Newsbeitrag
news:[email protected]

> Uh, you'd be suprised what a researcher would want to do. EG, one
> research bit I did loaded Xilinx designs after placement but before
> routing, ripped up all the registers, duplicated them for C-slowing,
> retimed, reinserted all the new registers, and wrote back out the
> placement.
>
> I could EASILY see an interesting research project which "meer mortal
> researchers" could attempt which would be take a bunch of easypath
> parts, map the actual defects, and route around defets albeit at a
> performance penalty.


As I said, I wont stop anyone.
But this looks like something for someone with too much free time on hands.
No offence intended ;-)

Regards
Falk



Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
Same Bitstream: Different Performance Adarsh Kumar Jain FPGA 3 10-14-2004 10:21 PM
Editing VCD file Robert Schopmeyer Verilog 0 12-19-2003 02:10 AM
editing a vcd file Narendran Kumaraguru Nathan Verilog 7 12-18-2003 08:12 PM


All times are GMT +1. The time now is 01:44 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved