FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 05-07-2006, 02:54 PM
YiQi
Guest
 
Posts: n/a
Default EDIFParser in JHDL / EDIF simulator?

Hi, all,

sorry if the question appears stupid, I just want to get it start.
also sorry about my poor english(it isn't my first language), hope you
can
understand what I mean.

My orignal design is done in VHDL. I have generate the edif from
Xilinx.
After reading most of the introduction, I think JHDL will be able to
help me
reading the EDIF file. What I try to do is read the EDIF file and
conver it
into my own structure (a chromosome of the circuit), follow by genetic
algorithm, to produce a new function with the circuit.

In my understanding, edif file captures the gates, FF, and wires only,
there
is not architecture dependent. Let me know if I am wrong.
Therefore, my questions are following:

1. Why do we need to specify the architecture(target) during VHDL ->
JHDL
using EDIFParser?

2. Because JHDL doesn't support asynchoronous loop. Is there any
software might do a better job than JHDL on simulating EDIF file as a
black box with VHDL? It will be even better if it can be done by scrpit
or command line (so that could be control by my java GA program)


Any help on this would be greatly appreciated.
Thanks very much in advance.

YiQi Huang

Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
JHDL Application baranwal FPGA 0 02-20-2006 09:02 PM
What does @ mean in EDIF? [email protected] FPGA 0 11-07-2005 07:22 PM
EDIF -> Map & Place -> EDIF ? Jacob Bower FPGA 13 12-03-2004 09:59 PM
VQM to EDIF krzychosz FPGA 1 02-23-2004 06:56 PM


All times are GMT +1. The time now is 07:56 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved