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  #1 (permalink)  
Old 08-12-2004, 06:43 PM
alastair
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Posts: n/a
Default Dual Microblaze System

Hi,

I'm trying to build a system with Xilinx EDK 3.2 which will have 2
Microblaze processors running separate code on a Virtex-II
(xc2v-1000).

In XPS, each microblaze component is attached to it's own data and
instruction LMB's which have BRAM and BRAM controller blocks attached
in turn. When I attempt to generate the bitstream, the process fails
during the map stage. I get the following error message:

ERROR:Pack:18 - The design is too large for the given device and
package.
Please check the Design Summary section to see which resource
requirement for
your design exceeds the resources available in the device.
..
..
..
Number of bonded IOBs: 132 out of 172 76%
Number of Tbufs: 1 out of 2,560 1%
Number of Block RAMs: 64 out of 40 160%
(OVERMAPPED)
Number of MULT18X18s: 6 out of 40 15%
Number of GCLKs: 1 out of 16 6%

So it looks to me like the number of block RAM's is where the problem
is. In the properties for each block ram, I've set the following
properties:
C_MEMSIZE = 8192
C_PORT_AWIDTH = 13

There is a total of 64k of block RAM available, so I figured that
allocating 8k to each processor should be fine.

If anyone has tried something similar I'd appreciate some ideas.

Thanks in advance,

Alastair.
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  #2 (permalink)  
Old 08-12-2004, 07:02 PM
Shalin Sheth
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Posts: n/a
Default Re: Dual Microblaze System

Alastair,

Check the memory mapping of all the Block RAM attached to the
processors. The mapping could be read from the following parameters of
the LMB Block RAM controllers:
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001fff

The above example is 8k of memory and will use 4 Block RAMs.

Shalin-

alastair wrote:
> Hi,
>
> I'm trying to build a system with Xilinx EDK 3.2 which will have 2
> Microblaze processors running separate code on a Virtex-II
> (xc2v-1000).
>
> In XPS, each microblaze component is attached to it's own data and
> instruction LMB's which have BRAM and BRAM controller blocks attached
> in turn. When I attempt to generate the bitstream, the process fails
> during the map stage. I get the following error message:
>
> ERROR:Pack:18 - The design is too large for the given device and
> package.
> Please check the Design Summary section to see which resource
> requirement for
> your design exceeds the resources available in the device.
> .
> .
> .
> Number of bonded IOBs: 132 out of 172 76%
> Number of Tbufs: 1 out of 2,560 1%
> Number of Block RAMs: 64 out of 40 160%
> (OVERMAPPED)
> Number of MULT18X18s: 6 out of 40 15%
> Number of GCLKs: 1 out of 16 6%
>
> So it looks to me like the number of block RAM's is where the problem
> is. In the properties for each block ram, I've set the following
> properties:
> C_MEMSIZE = 8192
> C_PORT_AWIDTH = 13
>
> There is a total of 64k of block RAM available, so I figured that
> allocating 8k to each processor should be fine.
>
> If anyone has tried something similar I'd appreciate some ideas.
>
> Thanks in advance,
>
> Alastair.


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  #3 (permalink)  
Old 08-13-2004, 04:18 AM
John Williams
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Posts: n/a
Default Re: Dual Microblaze System

Hi Alistair,

alastair wrote:

> I'm trying to build a system with Xilinx EDK 3.2 which will have 2
> Microblaze processors running separate code on a Virtex-II
> (xc2v-1000).


Firstly - if you possibly can, then upgrade to the latest version of
EDK. That's general advice, not specific to your question!

> In XPS, each microblaze component is attached to it's own data and
> instruction LMB's which have BRAM and BRAM controller blocks attached
> in turn. When I attempt to generate the bitstream, the process fails
> during the map stage. I get the following error message:


> Number of Block RAMs: 64 out of 40 160%


> So it looks to me like the number of block RAM's is where the problem
> is. In the properties for each block ram, I've set the following
> properties:
> C_MEMSIZE = 8192
> C_PORT_AWIDTH = 13
>
> There is a total of 64k of block RAM available, so I figured that
> allocating 8k to each processor should be fine.


Check to see if you are using caches for the microblaze - they are
implemented in BRAM. a 16K data and instruction cache will quickly chew
through your BRAM.

Also, if you grep through the *.srp files in the /synthesis project
subdirectory, you should be able to summarise the total BRAM usage:

Try this:

grep "Number.*BRAM" synthesis/*.srp

That will tell you exactly where you BRAM is going.

> If anyone has tried something similar I'd appreciate some ideas.


I've built a dual processor microblaze system before (two microblazes on
the same OPB bus, shared memory etc) and it synthesised without any
troubles for the XC2V1000. I can dig out the project files if you are
interested.

Cheers,

John
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  #4 (permalink)  
Old 08-13-2004, 12:06 PM
alastair
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Posts: n/a
Default Re: Dual Microblaze System

Guys,

Thanks for the advice - we're intending to update to the latest
version of the tools soon

It's been a while since I did any development with XPS (that's my
excuse) and after checking the memory map for the BRAM controllers I
get past the error I saw. Now I get another one when generating the
bitstream:

ERROR:Ncd:528 - Could not find the the corresponding NC_COMP for the
BlockRAM
instancename:<bram_lmb_2/bram_block_0_i/ramb16_s9_s9_0>.Cannot
continue with
BlockRAM updates.
ERROR:Bitgen:194 - Unable to update BRAM initialization data for
design
system.ncd.
make: *** [implementation/system.bit] Error 1
Done.

John - if you have time to dig out your project with dual processors
I'd appreciate being able to have a look at the setup. I'm not sure
what the error means and can't seem to find any information on the
error from a quick search on Google and the Xilinx website - any ideas
?

Thanks again,

Alastair.
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  #5 (permalink)  
Old 08-16-2004, 12:10 AM
John Williams
Guest
 
Posts: n/a
Default Re: Dual Microblaze System

Hi Alistair,

alastair wrote:

> It's been a while since I did any development with XPS (that's my
> excuse) and after checking the memory map for the BRAM controllers I
> get past the error I saw. Now I get another one when generating the
> bitstream:
>
> ERROR:Ncd:528 - Could not find the the corresponding NC_COMP for the
> BlockRAM
> instancename:<bram_lmb_2/bram_block_0_i/ramb16_s9_s9_0>.Cannot
> continue with
> BlockRAM updates.
> ERROR:Bitgen:194 - Unable to update BRAM initialization data for
> design
> system.ncd.
> make: *** [implementation/system.bit] Error 1
> Done.


Looks like the data2bram utility that stuffs bram contents onto the
bitstream, is having trouble distinguishing the various BRAMs. Did you
do a "make clean" after you fixed the initial error, and build it all
from scratch?

> John - if you have time to dig out your project with dual processors
> I'd appreciate being able to have a look at the setup. I'm not sure
> what the error means and can't seem to find any information on the
> error from a quick search on Google and the Xilinx website - any ideas


The MHS file is attached. This harwdare will build under 6.2, but I
don't think it will actually work. Note it's an SMP system, two
microblazes on the same bus which is not what you wanted. As such there
are other issues such as cache coherency (lack thereof), and no
interrupt sharing etc, but it's a starting point.

Cheers,

John

# Parameters
PARAMETER VERSION = 2.1.0

# Global Ports
PORT ext_clk = ext_clk, DIR = IN
PORT ddr_clk_fb = ddr_clk_fb, DIR = IN
PORT sys_rstn = sys_rstn, DIR = IN
PORT console_uart_rx = console_uart_rx, DIR = IN
PORT console_uart_tx = console_uart_tx, DIR = OUT
PORT debug_uart_rx = debug_uart_rx, DIR = IN
PORT debug_uart_tx = debug_uart_tx, DIR = OUT
PORT sram_cen = sram_cen, DIR = OUT, VEC = [0:1]
PORT sram_addr = sram_addr, DIR = OUT, VEC = [0:31]
PORT sram_ben = sram_ben, DIR = OUT, VEC = [0:3]
PORT sram_data = sram_data, DIR = INOUT, VEC = [0:31]
PORT sram_oen = sram_oen, DIR = OUT
PORT sram_wen = sram_wen, DIR = OUT
PORT sram_rst = sram_rst, DIR = OUT
PORT gpio = gpio, DIR = INOUT, VEC = [0:23]
PORT ddr_clk = ddr_clk, DIR = OUT
PORT ddr_clkn = ddr_clkn, DIR = OUT
PORT ddr_clke = ddr_clke, DIR = OUT
PORT ddr_csn = ddr_csn, DIR = OUT
PORT ddr_rasn = ddr_rasn, DIR = OUT
PORT ddr_casn = ddr_casn, DIR = OUT
PORT ddr_wen = ddr_wen, DIR = OUT
PORT ddr_dqm = ddr_dqm, DIR = OUT, VEC = [0:1]
PORT ddr_bankaddr = ddr_bankaddr, DIR = OUT, VEC = [0:1]
PORT ddr_addr = ddr_addr, DIR = OUT, VEC = [0:12]
PORT ddr_dq = ddr_dq, DIR = INOUT, VEC = [0:15]
PORT ddr_dqs = ddr_dqs, DIR = INOUT, VEC = [0:1]
PORT ETH_COL = ETH_COL, DIR = IN
PORT ETH_CRS = ETH_CRS, DIR = IN
PORT ETH_MDC = ETH_MDC, DIR = INOUT
PORT ETH_MDIO = ETH_MDIO, DIR = INOUT
PORT ETH_RXC = ETH_RXC, DIR = IN
PORT ETH_RXD = ETH_RXD, DIR = IN, VEC = [3:0]
PORT ETH_RXDV = ETH_RXDV, DIR = IN
PORT ETH_RXER = ETH_RXER, DIR = IN
PORT ETH_TXC = ETH_TXC, DIR = IN
PORT ETH_TXD = ETH_TXD, DIR = OUT, VEC = [3:0]
PORT ETH_TXEN = ETH_TXEN, DIR = OUT
PORT ETH_TXER = ETH_TXER, DIR = OUT
PORT PHY_RESETn = PHY_RESETn, DIR = OUT


# Sub Components
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER HW_VER = 2.00.a
PARAMETER C_USE_DIV = 0
PARAMETER C_USE_BARREL = 0
PARAMETER C_DEBUG_ENABLED = 0
PARAMETER C_USE_ICACHE = 1
PARAMETER C_ICACHE_BASEADDR = 0x80000000
PARAMETER C_ICACHE_HIGHADDR = 0x81FFFFFF
PARAMETER C_CACHE_BYTE_SIZE = 8192
PARAMETER C_ADDR_TAG_BITS = 11
BUS_INTERFACE DLMB = d_lmb_v10
BUS_INTERFACE ILMB = i_lmb_v10
BUS_INTERFACE DOPB = d_opb_v20
BUS_INTERFACE IOPB = d_opb_v20
PORT CLK = sys_clk
PORT INTERRUPT = interrupt
END

BEGIN microblaze
PARAMETER INSTANCE = microblaze_2
PARAMETER HW_VER = 2.00.a
PARAMETER C_USE_DIV = 0
PARAMETER C_USE_BARREL = 0
PARAMETER C_DEBUG_ENABLED = 0
PARAMETER C_USE_ICACHE = 1
PARAMETER C_ICACHE_BASEADDR = 0x80000000
PARAMETER C_ICACHE_HIGHADDR = 0x81FFFFFF
PARAMETER C_CACHE_BYTE_SIZE = 8192
PARAMETER C_ADDR_TAG_BITS = 11
BUS_INTERFACE DLMB = d2_lmb_v10
BUS_INTERFACE ILMB = i2_lmb_v10
BUS_INTERFACE DOPB = d_opb_v20
BUS_INTERFACE IOPB = d_opb_v20
PORT CLK = sys_clk
#PORT INTERRUPT = interrupt
END

# inverter to convert active low sys_rstn to active high sys_rst
BEGIN my_inverter
PARAMETER INSTANCE = rst_inverter
PORT I = sys_rstn
PORT O = sys_rst
END

BEGIN ddr_clk_gen
PARAMETER INSTANCE = my_ddr_clk_gen
PARAMETER HW_VER = 1.00.a
# 66mhz internal clock
PARAMETER C_CLKIN_PERIOD_NS = 15.0
# 66mhz external clock
PORT CLK_IN = clk66mhz
# tie DCM reset to system reset (active low)
PORT CLK_RST = sys_rst
# feedback from outside
PORT DDR_CLK_FB = ddr_clk_fb
# drive system clock with this one
PORT CLK0 = sys_clk
# 90 deg phase shifted system clock
PORT CLK90 = sys_clk_90
# external feedback 90 deg phase shift
PORT DDR_CLK_90 = ddr_clk_90
END

# PORT CORE_DCM_LOCKED = core_dcm_locked
# PORT DDR_DCM_LOCKED = ddr_dcm_locked
BEGIN opb_ddr
PARAMETER INSTANCE = ddr_controller
PARAMETER HW_VER = 1.00.b
# 100mhz clock
PARAMETER C_OPB_CLK_PERIOD_PS = 15000
PARAMETER C_INCLUDE_BURST_SUPPORT = 0
PARAMETER C_DQS_PULLUPS = 1
PARAMETER C_REG_DIMM = 0
PARAMETER C_DDR_TMRD = 15000
PARAMETER C_DDR_TWR = 15000
PARAMETER C_DDR_TWTR = 1
PARAMETER C_DDR_TRAS = 40000
PARAMETER C_DDR_TRC = 65000
PARAMETER C_DDR_TRFC = 75000
PARAMETER C_DDR_TRCD = 20000
PARAMETER C_DDR_TRRD = 15000
PARAMETER C_DDR_TREFC = 70000000
PARAMETER C_DDR_TREFI = 7800000
PARAMETER C_DDR_TRP = 20000
PARAMETER C_DDR_CAS_LAT = 2
PARAMETER C_DDR_DWIDTH = 16
PARAMETER C_DDR_AWIDTH = 13
PARAMETER C_DDR_COL_AWIDTH = 9
PARAMETER C_DDR_BANK_AWIDTH = 2
PARAMETER C_BASEADDR = 0x80000000
PARAMETER C_HIGHADDR = 0x81FFFFFF
BUS_INTERFACE SOPB = d_opb_v20
# system clock
PORT OPB_Clk = sys_clk
# phase shifted sys_clk
PORT Clk90_in = sys_clk_90
# phase shifted feedback clk
PORT DDR_Clk90_in = ddr_clk_90
# output clocks
PORT DDR_Clk = ddr_clk
# inverted clock
PORT DDR_Clkn = ddr_clkn
PORT DDR_CKE = ddr_clke
PORT DDR_CSn = ddr_csn
PORT DDR_RASn = ddr_rasn
PORT DDR_CASn = ddr_casn
PORT DDR_WEn = ddr_wen
PORT DDR_DM = ddr_dqm
PORT DDR_BankAddr = ddr_bankaddr
PORT DDR_Addr = ddr_addr
PORT DDR_DQ = ddr_dq
PORT DDR_DQS = ddr_dqs
END

BEGIN opb_memcon
PARAMETER INSTANCE = system_memcon
PARAMETER HW_VER = 1.00.a
PARAMETER C_OPB_CLOCK_PERIOD_PS = 15000
PARAMETER C_NUM_BANKS_MEM = 2
PARAMETER C_BASEADDR = 0xffff0000
PARAMETER C_HIGHADDR = 0xffff00ff
PARAMETER C_MEM0_BASEADDR = 0xffe00000
PARAMETER C_MEM0_HIGHADDR = 0xffefffff
PARAMETER C_MEM1_BASEADDR = 0xff000000
PARAMETER C_MEM1_HIGHADDR = 0xff7fffff
BUS_INTERFACE SOPB = d_opb_v20
PORT Mem_CEN = sram_cen
PORT Mem_A = sram_addr
PORT Mem_BEN = sram_ben
PORT Mem_DQ = sram_data
PORT Mem_OEN = sram_oen
PORT Mem_WEN = sram_wen
PORT OPB_Clk = sys_clk
PORT Mem_RPN = sram_rst
END

BEGIN opb_uartlite
PARAMETER INSTANCE = console_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_BAUDRATE = 57600
PARAMETER C_DATA_BITS = 8
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER C_CLK_FREQ = 66_666_667
PARAMETER C_BASEADDR = 0xFFFF2000
PARAMETER C_HIGHADDR = 0xFFFF20FF
BUS_INTERFACE SOPB = d_opb_v20
PORT Interrupt = console_uart_interrupt
PORT OPB_Clk = sys_clk
PORT RX = console_uart_rx
PORT TX = console_uart_tx
END

BEGIN opb_uartlite
PARAMETER INSTANCE = debug_uart
PARAMETER HW_VER = 1.00.b
PARAMETER C_DATA_BITS = 8
PARAMETER C_CLK_FREQ = 66_666_667
PARAMETER C_BAUDRATE = 115200
PARAMETER C_USE_PARITY = 0
PARAMETER C_ODD_PARITY = 0
PARAMETER C_BASEADDR = 0xFFFF4000
PARAMETER C_HIGHADDR = 0xFFFF40FF
BUS_INTERFACE SOPB = d_opb_v20
PORT Interrupt = debug_uart_interrupt
PORT OPB_Clk = sys_clk
PORT RX = debug_uart_rx
PORT TX = debug_uart_tx
END

BEGIN opb_intc
PARAMETER INSTANCE = system_intc
PARAMETER HW_VER = 1.00.c
PARAMETER C_BASEADDR = 0xffff3000
PARAMETER C_HIGHADDR = 0xffff30ff
BUS_INTERFACE SOPB = d_opb_v20
PORT Irq = interrupt
PORT OPB_Clk = sys_clk
PORT Intr = ethernet_interrupt & debug_uart_interrupt & console_uart_interrupt & timer_interrupt
END

BEGIN opb_timer
PARAMETER INSTANCE = system_timer
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0xffff1000
PARAMETER C_HIGHADDR = 0xffff10ff
BUS_INTERFACE SOPB = d_opb_v20
PORT OPB_Clk = sys_clk
PORT Interrupt = timer_interrupt
END

BEGIN opb_gpio
PARAMETER INSTANCE = system_gpio
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0xffff5000
PARAMETER C_HIGHADDR = 0xffff50ff
PARAMETER C_GPIO_WIDTH = 24
BUS_INTERFACE SOPB = d_opb_v20
PORT GPIO_IO = gpio
PORT OPB_Clk = sys_clk
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = d_lmb_bram_if_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001FFF
BUS_INTERFACE SLMB = d_lmb_v10
BUS_INTERFACE BRAM_PORT = conn_0
PORT LMB_Clk = sys_clk
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = i_lmb_bram_if_cntlr
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001FFF
BUS_INTERFACE SLMB = i_lmb_v10
BUS_INTERFACE BRAM_PORT = conn_1
PORT LMB_Clk = sys_clk
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = d_lmb_bram_if_cntlr2
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001FFF
BUS_INTERFACE SLMB = d2_lmb_v10
BUS_INTERFACE BRAM_PORT = conn_3
PORT LMB_Clk = sys_clk
END

BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = i_lmb_bram_if_cntlr2
PARAMETER HW_VER = 1.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x00001FFF
BUS_INTERFACE SLMB = i2_lmb_v10
BUS_INTERFACE BRAM_PORT = conn_4
PORT LMB_Clk = sys_clk
END

BEGIN bram_block
PARAMETER INSTANCE = bram
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEMSIZE = 8192
BUS_INTERFACE PORTA = conn_0
BUS_INTERFACE PORTB = conn_1
END

BEGIN bram_block
PARAMETER INSTANCE = bram2
PARAMETER HW_VER = 1.00.a
PARAMETER C_MEMSIZE = 8192
BUS_INTERFACE PORTA = conn_3
BUS_INTERFACE PORTB = conn_4
END

BEGIN opb_v20
PARAMETER INSTANCE = d_opb_v20
PARAMETER HW_VER = 1.10.b
PORT OPB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END

BEGIN lmb_v10
PARAMETER INSTANCE = i_lmb_v10
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END

BEGIN lmb_v10
PARAMETER INSTANCE = d_lmb_v10
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END

BEGIN lmb_v10
PARAMETER INSTANCE = i2_lmb_v10
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END

BEGIN lmb_v10
PARAMETER INSTANCE = d2_lmb_v10
PARAMETER HW_VER = 1.00.a
PORT LMB_Clk = sys_clk
PORT SYS_Rst = sys_rst
END

BEGIN my_dcm
PARAMETER INSTANCE = system_dcm
PARAMETER HW_VER = 1.00.a
PARAMETER C_CLKIN_PERIOD_NS = 10.0
PARAMETER C_DIVISOR = 3
PARAMETER C_INBUFFER = TRUE
PARAMETER C_MULTIPLIER = 2
PARAMETER C_OUTBUFFER = TRUE
# external clock input pin
PORT CLK_IN = ext_clk
PORT CLK_RST = net_gnd
PORT CLK_0 = clk_fb_o
PORT CLK_FB = clk_fb_i
# input to ddr_clk_gen module
PORT CLK_FX = clk66mhz
END

BEGIN my_bufg
PARAMETER INSTANCE = dcm_feedback_bufg
PORT I = clk_fb_o
PORT O = clk_fb_i
END

BEGIN opb_ethernet
PARAMETER INSTANCE = ether
PARAMETER HW_VER = 1.00.m
PARAMETER C_DMA_PRESENT = 1
PARAMETER C_DMA_INTR_COALESCE = 1
PARAMETER C_OPB_CLK_PERIOD_PS = 15000
PARAMETER C_BASEADDR = 0xC0000000
PARAMETER C_HIGHADDR = 0xC0003FFF
BUS_INTERFACE MSOPB = d_opb_v20
PORT OPB_Clk = sys_clk
PORT OPB_Rst = sys_rst
PORT PHY_col = ETH_COL
PORT PHY_crs = ETH_CRS
PORT PHY_Mii_clk = ETH_MDC
PORT PHY_Mii_data = ETH_MDIO
PORT PHY_rx_clk = ETH_RXC
PORT PHY_rx_data = ETH_RXD
PORT PHY_dv = ETH_RXDV
PORT PHY_rx_er = ETH_RXER
PORT PHY_tx_clk = ETH_TXC
PORT PHY_tx_data = ETH_TXD
PORT PHY_tx_en = ETH_TXEN
PORT PHY_tx_er = ETH_TXER
PORT PHY_rst_n = PHY_RESETn
PORT Freeze = net_gnd
PORT IP2INTC_Irpt = ethernet_interrupt
END


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  #6 (permalink)  
Old 08-16-2004, 05:07 PM
alastair
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Posts: n/a
Default Re: Dual Microblaze System

Hi John,

Thanks for posting the system - a combination of this and going
through my system with a careful eye got things working in the end
The final stumbling block was to make sure the reset signals for the
local memory buses were of the correct polarity.

Thanks again,

Alastair.
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