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Old 08-09-2006, 01:48 PM
Erik Verhagen
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Default DSP core, use of real type signals (Altera Stratix)

Hello,
I have a little problem, it is about real values in VHDL, and the way Quartus is managing them.
I am describing a simple DSP function (filter) in VHDL to implement on a Stratix device. As you probabely know, these functions need to shift input values in a register bank (declared as "signal" in VHDL), applying coefficients (reals) to them. These signals must therefor be of real type.
Quartus returns this error on compilation : <snip> Error (10414): VHDL error at iir_butterworth_3.vhd(49), at object "X": a real cannot be non-constant </snip> ("X" is such a register) Of course the filter coefficients (reals) are hardcoded as constants in a package, but these shift registers containing reals *are not* constants, they of course have to be signals to enable shifting.
I have read about obscure floating point units implemented on Stratix devices, so I suppose it should be possible to manage real signals (floating/fixed point representation ?) in it.
Does anyone have an idea about how I can use non-constant reals to create a DSP core on Stratix ? I think it is only a synthesis tool issue.

Here is the code (no comment on the casts, I *AM* aware this is not the most elegant)
A, B, C and D are the filter coefficients.
This description simulates PERFECTLY with Modelsim...

architecture testing of iir_butterworth_3 is

type register_bank is array (0 to 2) of real;
signal X : register_bank;
signal Y : register_bank;

begin

DSP : process(clock, reset, data_in)

begin

if reset = '1' then -- initialise registers to 0
for i in 0 to 2 loop
X(i) <= 0.0;
Y(i) <= 0.0;
end loop;

elsif clock'event AND clock = '1' then
X(0) <= real(conv_integer(data_in));
X(1 to 2) <= X(0 to 1); shift X's

Y(0) <= ( real(conv_integer(data_in)) + 3.0*X(0) + 3.0*X(1) + X(2) - B*Y(0) - C*Y(1) - D*Y(2)) / A;
Y(1 to 2) <= Y(0 to 1); shift Y's
end if;

end process DSP;

data_out <= conv_std_logic_vector(integer(Y(0)), data_width);

end architecture;


Thanks in advance for the help
Regards,


----------------------------------------------
- Erik Verhagen (div: AB-BI) -
- CERN, Geneva -
- European Organisation for Nuclear Research -
----------------------------------------------


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  #2 (permalink)  
Old 08-09-2006, 04:03 PM
Ray Andraka
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Posts: n/a
Default Re: DSP core, use of real type signals (Altera Stratix)

Erik Verhagen wrote:
> Hello,
> I have a little problem, it is about real values in VHDL, and the way Quartus is managing them.
> I am describing a simple DSP function (filter) in VHDL to implement on a Stratix device. As you probabely know, these functions need to shift input values in a register bank (declared as "signal" in VHDL), applying coefficients (reals) to them. These signals must therefor be of real type.
> Quartus returns this error on compilation : <snip> Error (10414): VHDL error at iir_butterworth_3.vhd(49), at object "X": a real cannot be non-constant </snip> ("X" is such a register) Of course the filter coefficients (reals) are hardcoded as constants in a package, but these shift registers containing reals *are not* constants, they of course have to be signals to enable shifting.
> I have read about obscure floating point units implemented on Stratix devices, so I suppose it should be possible to manage real signals (floating/fixed point representation ?) in it.
> Does anyone have an idea about how I can use non-constant reals to create a DSP core on Stratix ? I think it is only a synthesis tool issue.
>
> Here is the code (no comment on the casts, I *AM* aware this is not the most elegant)
> A, B, C and D are the filter coefficients.
> This description simulates PERFECTLY with Modelsim...
>
> architecture testing of iir_butterworth_3 is
>
> type register_bank is array (0 to 2) of real;
> signal X : register_bank;
> signal Y : register_bank;
>


> ----------------------------------------------
> - Erik Verhagen (div: AB-BI) -
> - CERN, Geneva -
> - European Organisation for Nuclear Research -
> ----------------------------------------------
>
>


Erik,

You are trying to work at too high a level of abstraction. The hardware
design is digital bits. You need to convert the real numbers into
something that maps into bits. The easier way hardware-wise is to
convert the reals (which are actually floating point values) to fixed
point, and then those can be treated as integers. The other option is
to construct floating point hardware and convert the real into a
floating point format where the bit fields are accessible to the hardware.

For fixed point, the inputs and coefficients are integers with an
implied scaling of 2^k where k can be any convenient constant (it has to
be constant for all input samples). For example 0.3333 could be
represented as 0x5555 in 16 bit fixed point representation if there is
an implied radix point to the left of the leftmost bit (ie, a scaling of
2^-16). 0x5555 = 21845 * 2^-16 = 0.3333

Floating point arithmetic dedicates a few bits to identifying the
position of the radix point. Here, there might a 24 bit mantissa plus
an 8 bit exponent. The value is interpreted as mantissa * 2^exponent.
Both the mantissa and exponent are represented as integers so that they
map into hardware with a finite number of bits. Floating point
arithmetic takes quite a bit more complicated logic to implement because
it requires tracking of the scale, as well as adjusting the scale of the
operands to keep the maximum accuracy. The current state of the
synthesis technology does not infer floating point arithmetic. In order
to use it, you will have to design the details or use somebody else's
floating point hardware library.

I'd suggest getting familiar with number representation before
attempting this project, as without a firm understanding of how the
numbers are represented and dealt with, you are going to have a tough
time completing the project successfully. You might consider finding a
copy of Isreal Koren's computer arithmetic algorithms book:
http://www.amazon.com/exec/obidos/AS...809002-4164633
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