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Old 04-18-2006, 11:48 PM
Sanka Piyaratna
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Default driving high speed ADC using an FPGA

Hi Everyone,

I am wondering if it would be possible to drive a 800 MHz 10 bit
parellel A/D using an FPGA which has a 100MHz system clock.

Thanks,

Sanka
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  #2 (permalink)  
Old 04-19-2006, 12:27 AM
John_H
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Default Re: driving high speed ADC using an FPGA

Probably. Budget also works into the decision.
Do you have your FPGA family or specific device already targeted?
Please consider driving your ADC clock from a clean source that doesn't
include the FPGA in the path; crosstalk from other I/O "near" a clock
generated by the FPGA will add jitter to your high speed clock that could be
detrimental to a very high performance system.

"Sanka Piyaratna" <[email protected]> wrote in message
news:[email protected]
> Hi Everyone,
>
> I am wondering if it would be possible to drive a 800 MHz 10 bit parellel
> A/D using an FPGA which has a 100MHz system clock.
>
> Thanks,
>
> Sanka



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  #3 (permalink)  
Old 04-19-2006, 02:31 AM
Ray Andraka
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Default Re: driving high speed ADC using an FPGA

Sanka Piyaratna wrote:
> Hi Everyone,
>
> I am wondering if it would be possible to drive a 800 MHz 10 bit
> parellel A/D using an FPGA which has a 100MHz system clock.
>
> Thanks,
>
> Sanka


I'm not sure what you mean by drive the ADC with the FPGA. The signal
flow is the other way around: the ADC will drive the FPGA. You should
not drive your ADC clocks from the FPGA. The jitter introduced by the
FPGA will absolutely kill the noise performance of the ADC at 800MHz.
At 100 MHz it will reduce the SNR to considerably less than the 10 bits.

Use a clean external clock to clock the ADC. Most high speed ADCs have
a clock output that can be fed to the FPGA to get a clean transfer of
the ADC data into the FPGA.
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  #4 (permalink)  
Old 04-19-2006, 10:29 AM
Venkat
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Default Re: driving high speed ADC using an FPGA

As Andraka pointed out, I guess you want your ADC Ouput connected to
the FPGA and if from what you mean the ADC is gonna sample at 800 Mhz
and you want the process those samples in your FPGA which can only work
at the max of 100 Mhz clock, the only way to do that is to use a DMUX
chip prior to the FPGA on board. There are DMUX chips available that
will demux 1:4 or 1:8 which also gives the slowed down data latch
signals (clock) which can be used as clock to latch the demux data
inside the FPGA.

Hope this helps.

Venkat.

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  #5 (permalink)  
Old 04-19-2006, 01:14 PM
Sanka Piyaratna
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Posts: n/a
Default Re: driving high speed ADC using an FPGA

Thank you very much everyone for your help. I was originally thinking of
the problem in the wrong way around. Now I understand what you mean. I
have not yet determined what parts to use. At this stage I am still
scoping the problem.

Thank you,

Sanka

Venkat wrote:
> As Andraka pointed out, I guess you want your ADC Ouput connected to
> the FPGA and if from what you mean the ADC is gonna sample at 800 Mhz
> and you want the process those samples in your FPGA which can only work
> at the max of 100 Mhz clock, the only way to do that is to use a DMUX
> chip prior to the FPGA on board. There are DMUX chips available that
> will demux 1:4 or 1:8 which also gives the slowed down data latch
> signals (clock) which can be used as clock to latch the demux data
> inside the FPGA.
>
> Hope this helps.
>
> Venkat.
>



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