FPGA Central

I've read much about Double Buffering, especially that it is good
practice (on Xilinx devices) to double buffer data signals (such as ADC
inputs), and place the double buffer in the IOB associated with the
pin.

Can someone explain to me, what double buffering is and why you would
use it? Any links to reference information would be appreciated.

Many thanks.

dh2006 schrieb:

> I've read much about Double Buffering, especially that it is good
> practice (on Xilinx devices) to double buffer data signals (such as ADC
> inputs), and place the double buffer in the IOB associated with the
> pin.
>
> Can someone explain to me, what double buffering is and why you would
> use it? Any links to reference information would be appreciated.
>
> Many thanks.
Double buffering is one way of syncronising signals which are being
passed between clock domains, primarily in order to prevent problems
with metastability.Its not only xilinx devices in which this is used
its used in any situation where signals which are asyncronous to some
logic need to be syncronised.There are other methods which can be used
to achieve the same thing.A google search on metestabilty will give you
further information.

[email protected] wrote:
> dh2006 schrieb:
>
>> I've read much about Double Buffering, especially that it is good
>> practice (on Xilinx devices) to double buffer data signals (such as ADC
>> inputs), and place the double buffer in the IOB associated with the
>> pin.
>>
>> Can someone explain to me, what double buffering is and why you would
>> use it? Any links to reference information would be appreciated.
>>
>> Many thanks.
> Double buffering is one way of syncronising signals which are being
> passed between clock domains, primarily in order to prevent problems
> with metastability.Its not only xilinx devices in which this is used
> its used in any situation where signals which are asyncronous to some
> logic need to be syncronised.There are other methods which can be used
> to achieve the same thing.A google search on metestabilty will give you
> further information.

.... and as an extra precision, "not only Xilinx devices" does not only
mean Altera's, Cypress and other programmable logic companies.
Double-registered async inputs are common fare in clocked digital
circuits of any sort, ASICs are not somehow magically exempted from this.

"dh2006" <[email protected]> wrote in message
news:[email protected] oups.com...
> I've read much about Double Buffering, especially that it is good
> practice (on Xilinx devices) to double buffer data signals (such as ADC
> inputs), and place the double buffer in the IOB associated with the
> pin.
> Can someone explain to me, what double buffering is and why you would
> use it? Any links to reference information would be appreciated.

"Double buffering" is a very vague term and means different things in
different contexts. Here are a few things it might mean in FPGA terms:

* Double-registering - as a previous poster pointed out, it is very common
to use two ranks of synchronizing flip-flops when moving from one clock
domain to another. This is a favourite topic in these parts so you'll have
no difficulty in finding an abundance of information about that. :-)

* Double data rate - many FPGAs nowadays have a special configuration
flip-flops to cater for DDR SDRAM and the like. These allow data to be clock
in and out to the external device on both edges of the reference clock,
while still permitting a single-clock design inside the FPGA itself. Refer
to your device datasheet to find out how these can be used.

* Double-buffering - say this to a designer of DSP or graphics processing
hardware and they will immediately think of a pair of RAM blocks being used
as a buffer between two processing elements in a so-called "ping pong"
configuration. This is a method for increasing the throughput of a system,
by allowing the data source to write a block of data to memory 'A' while the
data processing unit is reading the previous block from memory 'B'. When
both operations are done, A and B are swapped and the processing continues.

Judging from your use of the phrase "good practice", I think you are
probably refering to double-registering for synchronization. In which case,
do listen to the many experts who inhabit this group and you will likely
save yourself much pain and suffering!

Cheers,

-Ben-