Comments inline below... Basic summary is you need to think more like

hardware and less like software.

genlock (

[email protected]) wrote:

: Can you explain this logic that you have mentioned in more detail?

: I am using Xilinx ISE and when I try doing any division or

: multiplication, it keeps showing an error as follows:

: / can not have such operands in this context.

: ERROR: XST failed

: a)What I am trying to do is first convert the 24 bit vector to an

: integer.

: b)Then figure out a method to divide this integer by 1.36 that gives

: the result as an integer

: c)This integer is converted back to a 24 bit vector

Synthesis tools (ISE's XST etc.) use typecodes (and hence typecode

conversions) as a queue to how to implement something (e.g. signed or

unsigned multiply.) XST doesn't implement divides (other than by powers

of 2:-) full stop, so converting to a type where it's obvious to you

won't help the syn tool produce hardware. (It might work in simulation

though.)

Remember inside the

FPGA you are working with signals made of bits, and

only bits, so something like 1.36 is a bit meaningless. As others have

said just multiply by the reciprocal of the divisor. Below is an untested

code snippet to demonstrate how to do this in VHDL.

signal input : std_logic_vector(23 downto 0);

signal recip : std_logic_vector(23 downto 0);

signal mult_res: std_logic_vector(47 downto 0);

signal div_res : std_logic_vector(23 downto 0);

recip <= conv_std_logic(2^24 * 1 / 1.36) -- not sure this is the right

-- conv_blah function

-- Note that the calculation is

-- evaluated at synthesis time

mult_res <= input * recip -- assuming unsigned input

div_res <= mult_res(47 downto 24) -- there's a .5 bit rounding

-- error here for some results

Cheers,

Chris

: Any idea about how this division (b)can be performed?

: Thankyou