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  #1 (permalink)  
Old 12-19-2005, 04:21 PM
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Default Differential Pin Pairs in Lattice EC FPGAs

Hi newsgroup,

Altera has a command which is described as follows:

>The Show Differential Pin Pairs command shows a red connection line between a pair of >differential pins. When one of the pins is assigned to a node that has a differential I/O >standard assignment, the complementary pin is considered assigned and unavailable for >future pin assignments.


Does Lattice provide something similar for its EC/ECP familily ?

Rgds
André

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Old 12-19-2005, 04:31 PM
Antti Lukats
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Default Re: Differential Pin Pairs in Lattice EC FPGAs


<[email protected]> schrieb im Newsbeitrag
news:[email protected] oups.com...
Hi newsgroup,

Altera has a command which is described as follows:

>The Show Differential Pin Pairs command shows a red connection line between
>a pair of >differential pins. When one of the pins is assigned to a node
>that has a differential I/O >standard assignment, the complementary pin is
>considered assigned and unavailable for >future pin assignments.


Does Lattice provide something similar for its EC/ECP familily ?

Rgds
André

yes they do

antti


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Old 12-20-2005, 07:44 AM
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Default Re: Differential Pin Pairs in Lattice EC FPGAs

Hi Antti,

thank you for your answer. I forgot to ask what this
corresponding command is. ;o)
My search in the EC/ECP handbook was unsuccessful.

Rgds
André

>Antti Lukats wrote
>yes they do


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Old 12-20-2005, 07:48 AM
Antti Lukats
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Default Re: Differential Pin Pairs in Lattice EC FPGAs

<[email protected]> schrieb im Newsbeitrag
news:[email protected] ups.com...
Hi Antti,

thank you for your answer. I forgot to ask what this
corresponding command is. ;o)
My search in the EC/ECP handbook was unsuccessful.

Rgds
André

>Antti Lukats wrote
>yes they do


there is nothing special or nothing to know, just use diff prim and connect
one iopad the second will be autoassigned - thats it nothing special to
worry about

Antti


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  #5 (permalink)  
Old 12-20-2005, 08:35 AM
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Default Re: Differential Pin Pairs in Lattice EC FPGAs

Yes you are right, there is nothing special to worry about.
The Place and Route Report shows that the second IO is
reserved
whereas the Post-Place-and-Route Floorplanner does not
show any connection between the two IOs. But it should
be assumed that the connection does exist ...

Rgds
André

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