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  #1 (permalink)  
Old 01-30-2007, 12:18 PM
Thomas Reinemann
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Default Differential pairs per Bank

Hello,

we want to use a Spartan-3A to collect signals of about 100
differential lines. This type offers the possibility for on-chip LVDS
termination. Is there a limit how many pairs per bank can be
terminated via the on-chip resistor? Where may I find further
information?

Thanks Tom

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  #2 (permalink)  
Old 01-30-2007, 07:03 PM
Sean Durkin
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Default Re: Differential pairs per Bank

Thomas Reinemann wrote:
> Hello,
>
> we want to use a Spartan-3A to collect signals of about 100
> differential lines. This type offers the possibility for on-chip LVDS
> termination. Is there a limit how many pairs per bank can be
> terminated via the on-chip resistor?

I'm not really fluent in the Spartan-3A-architecture, but if it's
anything like Virtex, then there should be no limit. The only
restriction is that for some I/O-pins in a bank, there is no second pin
for the differential pair, i.e. some pins can only be used single-ended.
So the overall total of differential pairs you can use in the FPGA does
not equal the total number of IOs/2.

But in Spartan-3A, your VCCO needs to be 3.3V if you want the internal
terminations to be 100R (see page 339 of ug331 from Dec 5, 2006).
Strange enough, in Spartan-3E, Virtex-II Pro and Virtex-4, VCCO needs to
be 2.5V for the correct termination value, so this is something one has
to look out for.

As I found out after installing on Friday, ISE9.1 stops the place and
route with an error message if you don't watch out for this. In earlier
versions of the tools, this did not even produce a warning.

--
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...
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  #3 (permalink)  
Old 01-30-2007, 08:14 PM
Uwe Bonnes
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Default Re: Differential pairs per Bank

Thomas Reinemann <[email protected]> wrote:
> Hello,


> we want to use a Spartan-3A to collect signals of about 100
> differential lines. This type offers the possibility for on-chip LVDS
> termination. Is there a limit how many pairs per bank can be
> terminated via the on-chip resistor? Where may I find further
> information?


Often LVDS on-chip Termination is a power hog on Xilinx chips.
Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It
eases layout and spares you a lot of pins.

--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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  #4 (permalink)  
Old 01-31-2007, 10:13 AM
Symon
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Default Re: Differential pairs per Bank

"Uwe Bonnes" <[email protected]> wrote in message
news:[email protected]
> Thomas Reinemann <[email protected]> wrote:
>> Hello,

>
>> we want to use a Spartan-3A to collect signals of about 100
>> differential lines. This type offers the possibility for on-chip LVDS
>> termination. Is there a limit how many pairs per bank can be
>> terminated via the on-chip resistor? Where may I find further
>> information?

>
> Often LVDS on-chip Termination is a power hog on Xilinx chips.
> Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It
> eases layout and spares you a lot of pins.
>

Hi Uwe,
Are you saying that LVDS uses more power than LVDS_DT from the Xilinx
supplies? That surprises me. Could you point me in the direction of some
documentation for this? Or maybe you're refering to the DCI modes?
Thanks, Syms.


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  #5 (permalink)  
Old 01-31-2007, 10:36 AM
Uwe Bonnes
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Default Re: Differential pairs per Bank

Symon <[email protected]> wrote:
> "Uwe Bonnes" <[email protected]> wrote in message
> news:[email protected]
> > Thomas Reinemann <[email protected]> wrote:
> >> Hello,

> >
> >> we want to use a Spartan-3A to collect signals of about 100
> >> differential lines. This type offers the possibility for on-chip LVDS
> >> termination. Is there a limit how many pairs per bank can be
> >> terminated via the on-chip resistor? Where may I find further
> >> information?

> >
> > Often LVDS on-chip Termination is a power hog on Xilinx chips.
> > Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It
> > eases layout and spares you a lot of pins.
> >

> Hi Uwe,
> Are you saying that LVDS uses more power than LVDS_DT from the Xilinx
> supplies? That surprises me. Could you point me in the direction of some
> documentation for this? Or maybe you're refering to the DCI modes?
> Thanks, Syms.


I meant the problem with excessive power for LVDS with on-chip DCI
termination.
--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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  #6 (permalink)  
Old 02-04-2007, 10:42 AM
Ben Popoola
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Default Re: Differential pairs per Bank

Uwe Bonnes wrote:
> Symon <[email protected]> wrote:
>> "Uwe Bonnes" <[email protected]> wrote in message
>> news:[email protected]
>>> Thomas Reinemann <[email protected]> wrote:
>>>> Hello,
>>>> we want to use a Spartan-3A to collect signals of about 100
>>>> differential lines. This type offers the possibility for on-chip LVDS
>>>> termination. Is there a limit how many pairs per bank can be
>>>> terminated via the on-chip resistor? Where may I find further
>>>> information?
>>> Often LVDS on-chip Termination is a power hog on Xilinx chips.
>>> Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It
>>> eases layout and spares you a lot of pins.
>>>

>> Hi Uwe,
>> Are you saying that LVDS uses more power than LVDS_DT from the Xilinx
>> supplies? That surprises me. Could you point me in the direction of some
>> documentation for this? Or maybe you're refering to the DCI modes?
>> Thanks, Syms.

>
> I meant the problem with excessive power for LVDS with on-chip DCI
> termination.


Be careful also that you do not fry the Spartan 3A when you use DCI
termination for 100 differential lines as all the power dissipated will
be within the chip. The advantage of using external termination
resistors or LVDS devices is that the power is not dissipated within the
FPGA.


Ben
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  #7 (permalink)  
Old 02-04-2007, 06:33 PM
Peter Alfke
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Default Re: Differential pairs per Bank

Why speculate when it is all described in the appropriate user guide?
The differential termination is internal, and consumes hardly any
power, since it is truly differential, not the fake differential power
hog implemented in DCI.
And UG331 on page 338/339 clearly states that you can use either 3.3
or 2.5 V (but at 2.5 V the differential termination resistor is not as
precise a value).

Peter Alfke
==========================
On Jan 30, 12:14 pm, Uwe Bonnes <[email protected]
darmstadt.de> wrote:
> Thomas Reinemann <[email protected]> wrote:
> > Hello,
> > we want to use a Spartan-3A to collect signals of about 100
> > differential lines. This type offers the possibility for on-chip LVDS
> > termination. Is there a limit how many pairs per bank can be
> > terminated via the on-chip resistor? Where may I find further
> > information?

>
> Often LVDS on-chip Termination is a power hog on Xilinx chips.
> Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It
> eases layout and spares you a lot of pins.
>
> --
> Uwe Bonnes [email protected]
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------



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  #8 (permalink)  
Old 02-04-2007, 08:08 PM
John_H
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Posts: n/a
Default Re: Differential pairs per Bank

Ben Popoola wrote:
> Uwe Bonnes wrote:
>> Symon <[email protected]> wrote:
>>> "Uwe Bonnes" <[email protected]> wrote in message
>>> news:[email protected]
>>>> Thomas Reinemann <[email protected]> wrote:
>>>>> Hello,
>>>>> we want to use a Spartan-3A to collect signals of about 100
>>>>> differential lines. This type offers the possibility for on-chip LVDS
>>>>> termination. Is there a limit how many pairs per bank can be
>>>>> terminated via the on-chip resistor? Where may I find further
>>>>> information?
>>>> Often LVDS on-chip Termination is a power hog on Xilinx chips.
>>>> Consider using a multi channel LVDS transceiver. like the
>>>> SN65LVDM1677. It
>>>> eases layout and spares you a lot of pins.
>>>>
>>> Hi Uwe,
>>> Are you saying that LVDS uses more power than LVDS_DT from the Xilinx
>>> supplies? That surprises me. Could you point me in the direction of
>>> some documentation for this? Or maybe you're refering to the DCI modes?
>>> Thanks, Syms.

>>
>> I meant the problem with excessive power for LVDS with on-chip DCI
>> termination.

>
> Be careful also that you do not fry the Spartan 3A when you use DCI
> termination for 100 differential lines as all the power dissipated will
> be within the chip. The advantage of using external termination
> resistors or LVDS devices is that the power is not dissipated within the
> FPGA.
>
>
> Ben


Only the Spartan-3 offers DCI - not Spartan-3A, not even Spartan-3E.
The DIFF_TERM is offered in the 3A and 3E but DCI is expected for the
Spartan-3 base family only. Starting with the Virtex-2Pro (it appears,
from an Austin Lesea response back in early 2004) the LVDS_DT uses "a
true differential termination (a resistor) that is switched in
between + and - inputs" which shouldn't take up *any* significant power.

http://groups.google.com/group/comp....735c3ecf07621?
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