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  #1 (permalink)  
Old 05-12-2006, 10:19 AM
YiQi
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Default difference of variable and signal

What's the different between variable and signal?

variable
signal
assignment operator: :=
<=
share between process: key word"shared"
yes

what else?

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  #2 (permalink)  
Old 05-12-2006, 10:51 PM
Jim_B
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Default Re: difference of variable and signal


Sounds like an interview question.
There are a lot more differences, which go basically down to the
concepts of VHDL. You can write pages about this. This is one of the
best and most difficult to answer questions about VHDL IMHO.

YiQi wrote:
> What's the different between variable and signal?
>
> variable
> signal
> assignment operator: :=
> <=
> share between process: key word"shared"
> yes
>
> what else?
>

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  #3 (permalink)  
Old 05-13-2006, 07:32 AM
YiQi
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Default Re: difference of variable and signal

thx, Jim,
Sorry, the examples are miss leading. My main concern is the different
during design flow.
Let me restate my question, During HDL synthesis, that's the difference
between them?
Will that make any different after synthesis(place & route)?

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  #4 (permalink)  
Old 05-15-2006, 01:02 PM
Falk Salewski
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Default Re: difference of variable and signal

variable: store information in a memory cell
signal: "wire" to send information to other modules
if the information in signal is needed later on, a latch is
put in the signal line

"YiQi" <[email protected]> schrieb im Newsbeitrag
news:[email protected] oups.com...
> thx, Jim,
> Sorry, the examples are miss leading. My main concern is the different
> during design flow.
> Let me restate my question, During HDL synthesis, that's the difference
> between them?
> Will that make any different after synthesis(place & route)?
>



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  #5 (permalink)  
Old 05-15-2006, 02:23 PM
Falk Brunner
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Default Re: difference of variable and signal

Falk Salewski schrieb:

> variable: store information in a memory cell
> signal: "wire" to send information to other modules
> if the information in signal is needed later on, a latch is
> put in the signal line


I doubt it. There are plenty of signals in every HDL design without any
latch. As someone pointed out before, it's a complicated story (and so
answer) of HDL principles.

Regards
Falk
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  #6 (permalink)  
Old 05-15-2006, 03:01 PM
YiQi
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Default Re: difference of variable and signal

Thanks both Falk,
In a FPGA, does a latch and a memory cell make any different? Isn't it
the same ?

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  #7 (permalink)  
Old 05-15-2006, 03:22 PM
Ralf Hildebrandt
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Default Re: difference of variable and signal

YiQi wrote:

> In a FPGA, does a latch and a memory cell make any different? Isn't it
> the same ?



In most FPGAs there are no latches. You should avoid inferring latches
in these FPGAs, because they are created out of logic gates.

Black-RAM in FPGAs can often be accessed using the edge of a signal. ->
No Latches.

For standard cells you may use latches to get a compatible behavior to
standard DRAM.

DRAM is one capacitor and one transistor. Latches are closed loops build
out of logic gates.

Ralf
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