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Old 12-29-2003, 09:21 PM
toomuch
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Posts: n/a
Default A difference between VHDL sources working

Hi

Can someone tell me if there is a defference between the following two VHDL
sources working:
1.
process
begin
wait until C'event and C='1';
if B='0' then
Q<=B;
else
Q<= A;
end if;
end process;

2.
process
begin
if B='0' then
wait until C'event and C='1';
Q<=B;
else
wait until C'event and C='1';
Q<=A;
end if;
end process;


Simulation of this two processes gives different results. Does anybody know
why? Is there a specification discussing those cases?

Thanks for any help



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  #2 (permalink)  
Old 12-30-2003, 12:52 AM
David R Brooks
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Posts: n/a
Default Re: A difference between VHDL sources working

It's apparent from the code:
Case 1 says "wait for clock, THEN test B and act accordingly"
Case 2 says "Test B, decide how to act, THEN wait for clock"

Also, Case A is synthesisable (being a register with a 2-input mux in
front), case B is probably not synthesisable (ie there is no hardware
equivalent).

"toomuch" <[email protected]> wrote:

:Hi
:
:Can someone tell me if there is a defference between the following two VHDL
:sources working:
:1.
rocess
:begin
: wait until C'event and C='1';
: if B='0' then
: Q<=B;
: else
: Q<= A;
: end if;
:end process;
:
:2.
rocess
:begin
: if B='0' then
: wait until C'event and C='1';
: Q<=B;
: else
: wait until C'event and C='1';
: Q<=A;
: end if;
:end process;
:
:
:Simulation of this two processes gives different results. Does anybody know
:why? Is there a specification discussing those cases?
:
:Thanks for any help
:
:

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  #3 (permalink)  
Old 12-30-2003, 02:15 AM
Allan Herriman
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Posts: n/a
Default Re: A difference between VHDL sources working

On Mon, 29 Dec 2003 21:21:55 +0100, "toomuch" <[email protected]>
wrote:

>Hi
>
>Can someone tell me if there is a defference between the following two VHDL
>sources working:
>1.
>process
>begin
> wait until C'event and C='1';
> if B='0' then
> Q<=B;
> else
> Q<= A;
> end if;
>end process;
>
>2.
>process
>begin
> if B='0' then
> wait until C'event and C='1';
> Q<=B;
> else
> wait until C'event and C='1';
> Q<=A;
> end if;
>end process;
>
>
>Simulation of this two processes gives different results.


Yes.

>Does anybody know why?


Yes.

1 samples B and A just after the rising edge of C.

2 samples B and A just after the rising edge of C, but doesn't use the
value of B until after the next rising edge of C.

2 is not good coding style. Don't have more than one wait statement
in a synthesisable process.

>Is there a specification discussing those cases?


Yes. Try: The VHDL LRM. Any VHDL text book. Any VHDL lecture notes.
The VHDL FAQ. Google.

Regards,
Allan.
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