FPGA Central

Greetings everyone,

I've recently started working on FPGA designs and was wondering if
there is a way to get timing reports and synthesis results from the
Xilinx software that don't include I/O pin mapping. I'm trying to
constrain several blocks for testing purposes, but these modules will
all be internal to the design and won't be connected directly to the
pins. However, it seems the tools automaically assume these
connections, which is adding extra delay than what will really be
there. Is there a way to tell the tool to ignore physical pin
connections and use, say, simulated register I/O connections instead?

Sorry if this seems like a silly question, I'm still getting the hang
of synthesis yet.

Thanks in advance,
Jeremy

Jeremy Wood wrote:
> Greetings everyone,
>
> I've recently started working on FPGA designs and was wondering if
> there is a way to get timing reports and synthesis results from the
> Xilinx software that don't include I/O pin mapping. I'm trying to
> constrain several blocks for testing purposes, but these modules will
> all be internal to the design and won't be connected directly to the
> pins. However, it seems the tools automaically assume these
> connections, which is adding extra delay than what will really be
> there. Is there a way to tell the tool to ignore physical pin
> connections and use, say, simulated register I/O connections instead?
>
> Sorry if this seems like a silly question, I'm still getting the hang
> of synthesis yet.
>
> Thanks in advance,
> Jeremy

Hi Jeremy,

Under Synthesis properties (right hand click synthesis in the tool chain
view), select the Xilinx Specific Options tab then untick "Add I/O
buffers" and you should be where you want to be!

As a note you may also wish to select "Advanced options" to allow more
control over the tools (from the menu bar Edit > Preferences > Processes
> PropertyDisplayLevel change to Advanced).

However, more realistic timing can often be obtained by placing you
design unit (presumably will ultimately be located deep within your
design, eg a super fast multiplier) between registers, adding timing
constraints and use the static timing report....

All the best,

Tim

Tim Good wrote:

> Jeremy Wood wrote:
>
>> Greetings everyone,
>>
>> I've recently started working on FPGA designs and was wondering if
>> there is a way to get timing reports and synthesis results from the
>> Xilinx software that don't include I/O pin mapping. I'm trying to
>> constrain several blocks for testing purposes, but these modules will
>> all be internal to the design and won't be connected directly to the
>> pins. However, it seems the tools automaically assume these
>> connections, which is adding extra delay than what will really be
>> there. Is there a way to tell the tool to ignore physical pin
>> connections and use, say, simulated register I/O connections instead?
>>
>> Sorry if this seems like a silly question, I'm still getting the hang
>> of synthesis yet.
>>
>> Thanks in advance,
>> Jeremy
>
>
> Hi Jeremy,
>
> Under Synthesis properties (right hand click synthesis in the tool
> chain view), select the Xilinx Specific Options tab then untick "Add
> I/O buffers" and you should be where you want to be!
>
> As a note you may also wish to select "Advanced options" to allow more
> control over the tools (from the menu bar Edit > Preferences >
> Processes > PropertyDisplayLevel change to Advanced).
>
> However, more realistic timing can often be obtained by placing you
> design unit (presumably will ultimately be located deep within your
> design, eg a super fast multiplier) between registers, adding timing
> constraints and use the static timing report....
>
> All the best,
>
> Tim

Just want to add, when you disable IO to be added by XST you need to let
MAP know not to trim out all the design (for MAP a design with no
external connections doesn't make sense) by giving -u as a comand line
option, or from ISE by displaying the MAP process proprieties and
disable the "Trim unconnected signals".

Aurash

--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/

phone: 353 01 4032639
fax: 353 01 4640324

Thanks for the help guys, its exactly what I was looking for.

And Tim is right, I won't be getting realistic timing results unless I
load my inputs and outputs with registers. But at least I won't have
to worry about 132 I/O pin mappings that won't even be there affecting
my delay.

Thanks again

Jeremy

> However, more realistic timing can often be obtained by placing you design unit (presumably will ultimately be located deep within
> your design, eg a super fast multiplier) between registers, adding timing constraints and use the static timing report....
>

For this kind of exercise I usually use even two registers between
the pins and the DUT. When the P&R places the first register in the
IO pad the second register avoids a probably long path from the IO
to the DUT (assuming that the second register gets placed near the
DUT).

Another tip: If you have more input and output signals than pins just
add more registers and use signals from different pipeline stages.
Synthesizer are (not yet) smart enough to optimize this away ;-)

Martin