FPGA Central - World's 1st FPGA / CPLD Portal

FPGA Central

World's 1st FPGA Portal

 

Go Back   FPGA Groups > NewsGroup > FPGA

FPGA comp.arch.fpga newsgroup (usenet)

Reply
 
LinkBack Thread Tools Display Modes
  #1 (permalink)  
Old 05-13-2004, 12:41 AM
azcycle
Guest
 
Posts: n/a
Default Decompiler for GAL JEDEC fusemap

Hi,

Is anyone aware of a equation decompiler for GAL devices? I'm looking for a
program that can take a GAL JEDEC fuse map file and decompile it to its
source logic equations. I know this can be done manually but that can be
very tedious and error prone.

Thanks,

Steve


Reply With Quote
  #2 (permalink)  
Old 05-13-2004, 12:44 AM
Jim Granville
Guest
 
Posts: n/a
Default Re: Decompiler for GAL JEDEC fusemap

azcycle wrote:
> Hi,
>
> Is anyone aware of a equation decompiler for GAL devices? I'm looking for a
> program that can take a GAL JEDEC fuse map file and decompile it to its
> source logic equations. I know this can be done manually but that can be
> very tedious and error prone.


Google for JED2EQN
-jg

Reply With Quote
  #3 (permalink)  
Old 05-13-2004, 01:00 AM
azcycle
Guest
 
Posts: n/a
Default Re: Decompiler for GAL JEDEC fusemap

Thanks,

I'll check it out.

Steve
"Jim Granville" <[email protected]> wrote in message
news:[email protected]
> azcycle wrote:
> > Hi,
> >
> > Is anyone aware of a equation decompiler for GAL devices? I'm looking

for a
> > program that can take a GAL JEDEC fuse map file and decompile it to its
> > source logic equations. I know this can be done manually but that can be
> > very tedious and error prone.

>
> Google for JED2EQN
> -jg
>



Reply With Quote
Reply

Bookmarks

Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are On
Pingbacks are On
Refbacks are On


Similar Threads
Thread Thread Starter Forum Replies Last Post
from jedec to schematic ?? blisca FPGA 0 10-11-2003 08:54 AM
Convert Jedec to logical equations yusuke FPGA 3 08-29-2003 06:14 AM


All times are GMT +1. The time now is 03:30 AM.


Powered by vBulletin® Version 3.8.0
Copyright ©2000 - 2020, Jelsoft Enterprises Ltd.
Search Engine Friendly URLs by vBSEO 3.2.0
Copyright 2008 @ FPGA Central. All rights reserved