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Old 11-04-2007, 07:34 PM
maxascent
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Default DDR2 Interface


Hi

I am designing a board with a Virex 4 and a DDR2 component. I have use
the MIG tool to generate an interface. However the pinout it has generte
is not ideal as there are a lot of crossed nets. Can I tweak the nets t
give me better routing or will this leave me with a non working interface
I cant really see any reason why it still wouldn't work.

Cheers

Jon
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Old 11-04-2007, 09:41 PM
austin
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Default Re: DDR2 Interface

Jon,

Did you create or edit the UCF (user constraint file) as noted in:

http://direct.xilinx.com/bvdocs/whitepapers/wp260.pdf

Step 2 of the flow chart?

This is where you choose the pins you want to use (constraint eh design
to use the pins you would like to use).

If you don't chose, the tools will choose for you. If you choose pins
that can not work, the tools will tell you that timing can't be met.

For example, choice of pins that should be together (like a data bus)
need to be in the same bank, or for wide interfaces, adjacent banks.

Austin
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